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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
sifive
Age
Commit message (
Expand
)
Author
Files
Lines
2020-10-16
clk: sifive: Include device_compat.h
Sean Anderson
1
-7
/
+7
2020-08-04
sifive: reset: add DM based reset driver for SiFive SoC's
Sagar Shrikant Kadam
1
-15
/
+58
2020-08-04
fu540: prci: use common reset indexes defined in binding header
Sagar Shrikant Kadam
1
-10
/
+7
2020-06-04
clk: sifive: fu540-prci: Release ethernet clock reset
Pragnesh Patel
1
-0
/
+20
2020-06-04
clk: sifive: fu540-prci: Add ddr clock initialization
Pragnesh Patel
1
-6
/
+45
2020-06-04
clk: sifive: fu540-prci: Add clock enable and disable ops
Pragnesh Patel
1
-12
/
+96
2020-05-19
common: Drop linux/delay.h from common header
Simon Glass
1
-0
/
+1
2020-02-06
dm: core: Require users of devres to include the header
Simon Glass
1
-0
/
+1
2019-07-19
clk: sifive: Drop GEMGXL clock driver
Anup Patel
3
-69
/
+0
2019-07-19
clk: sifive: Sync-up main driver with upstream Linux
Anup Patel
1
-36
/
+60
2019-07-19
clk: sifive: Sync-up DT bindings header with upstream Linux
Anup Patel
1
-1
/
+1
2019-07-19
clk: sifive: Sync-up WRPLL library with upstream Linux
Anup Patel
1
-13
/
+13
2019-07-19
clk: sifive: Factor-out PLL library as separate module
Anup Patel
5
-498
/
+1
2019-06-01
clk: sifive: Add clock driver for GEMGXL MGMT
Bin Meng
3
-0
/
+69
2019-05-08
clk: sifive: fu540-prci: Change include order
Jagan Teki
1
-1
/
+1
2019-02-27
clk: Add SiFive FU540 PRCI clock driver
Anup Patel
5
-0
/
+1119