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path: root/drivers/clk/sunxi
AgeCommit message (Expand)AuthorFilesLines
2019-07-16sunxi: clocks: Add H6 USB clock gates and resetsAndre Przywara1-0/+29
2019-04-16clk: sunxi: r40: Fix GMAC reset reg offsetJagan Teki1-1/+2
2019-04-01clk: sunxi: a10: Add CLK_AHB_GMACJagan Teki1-0/+2
2019-03-09clk: sunxi: h3: Implement EPHY CLK and RESETJagan Teki1-0/+4
2019-03-09clk: sunxi: Implement EMAC, GMAC clocks, resetsJagan Teki6-0/+15
2019-03-09clk: sunxi: Implement A10 EMAC clocksJagan Teki2-0/+2
2019-03-04clk: sunxi: Implement SPI clocks, resetsJagan Teki11-0/+97
2019-01-30sunxi: clk: enable clk and reset for CCU devicesAndre Przywara1-0/+12
2019-01-29sunxi: clk: A80: add MMC clock supportAndre Przywara1-1/+27
2019-01-29sunxi: clk: add MMC gates/resetsAndre Przywara11-0/+63
2019-01-18clk: sunxi: Add Allwinner A80 CLK driverJagan Teki3-0/+65
2019-01-18clk: sunxi: Add Allwinner H6 CLK driverJagan Teki3-0/+61
2019-01-18clk: sunxi: Implement UART resetsJagan Teki7-0/+43
2019-01-18clk: sunxi: Implement UART clocksJagan Teki9-0/+57
2019-01-18clk: sunxi: Add Allwinner V3S CLK driverJagan Teki3-0/+59
2019-01-18clk: sunxi: Add Allwinner R40 CLK driverJagan Teki3-0/+78
2019-01-18clk: sunxi: Add Allwinner A83T CLK driverJagan Teki3-0/+71
2019-01-18clk: sunxi: Add Allwinner A23/A33 CLK driverJagan Teki3-0/+71
2019-01-18clk: sunxi: Add Allwinner A31 CLK driverJagan Teki3-0/+76
2019-01-18clk: sunxi: Add Allwinner A10s/A13 CLK driverJagan Teki3-0/+64
2019-01-18clk: sunxi: Add Allwinner A10/A20 CLK driverJagan Teki3-0/+67
2019-01-18clk: sunxi: Add Allwinner H3/H5 CLK driverJagan Teki3-0/+87
2019-01-18reset: Add Allwinner RESET driverJagan Teki2-0/+21
2019-01-18clk: Add Allwinner A64 CLK driverJagan Teki4-0/+147