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path: root/drivers/clk
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2021-05-21clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12Marek Vasut5-9/+6
Synchronize R-Car Gen2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Synchronize RZ/G2 tables with Linux 5.12Marek Vasut3-5/+26
Synchronize RZ/G2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-14clk: Add support for the k210 clock driver pre-relocationSean Anderson1-4/+10
Variables which had previously been stored in .bss are moved to .data. In addition, probed needs to be reset when the clock driver is re-bound post-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Move the clint clock to under aclkSean Anderson1-1/+1
No other (real) clocks have the cpu clock as their parent; instead they are children of aclk. Move the clint clock under aclk to match them. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Remove k210_register_pllSean Anderson2-28/+3
This simplifies the PLL creation process, since we don't have to pass all the parameters individually. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Fix PLL enable always getting takenSean Anderson1-1/+2
This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14clk: k210: Fix PLLs not being enabledSean Anderson1-0/+2
After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
2021-05-14clk: Warn on failure to assign rateSean Anderson1-4/+7
If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-12clk: ti: am3-dpll: use custom API for memory accessDario Binacchi1-33/+53
Using the custom TI functions required not only replacing common memory access functions but also rewriting the routines used to set bypass and lock states. As for readl() and writel(), they also required the address of the register to be accessed, a parameter that is hidden by the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12clk: ti: gate: use custom API for memory accessDario Binacchi1-11/+12
Replaces the common memory access functions used by the driver with the ones exported from the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12clk: ti: change clk_ti_latch() signatureDario Binacchi4-24/+28
The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12clk: ti: add custom API for memory accessDario Binacchi2-0/+98
As pointed by [1] and [2], commit d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong: - It makes every 'reg' DT property translatable. It changes the address translation so that for an I2C 'reg' address you'll get back as reg the I2C controller address + reg value. - The quirk must be fixed with platform code. The clk_ti_get_reg_addr() is the platform code able to make the correct address translation for the AM33xx clocks registers. Its implementation was inspired by the Linux Kernel code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-04-29Merge tag 'xilinx-for-v2021.07-rc2' of ↵Tom Rini1-1/+1
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.07-rc2 xilinx: - Enable saving variables based on bootmode - Cleanup usb dfu setup and wire it up with usb bootmode - Fix bootscript address logic - Remove GD references (spi, Versal) - Enable capsule update clk: - Small Kconfig fix net: - Fix gmii2rgmii bridge binding usb: - Propagate error (dfu gadget)
2021-04-26clk: renesas: Synchronize Gen2 MSTP teardown tablesMarek Vasut3-6/+6
Synchronize Gen2 MSTP teardown tables with datasheet Rev.2.00 Feb 01, 2016. This corrects the following bits: - added H2 MSTP3[10] SCIF2 - added H2/M2/E2 MSTP7[29] TCON - removed E2 MSTP5[22] Thermal Sensor - removed E2 MSTP10[31,24:22] SRC0, SRC7:9 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-04-26clk: renesas: Only ever access documented bits in clock driver teardownMarek Vasut7-81/+81
The clock driver used a heavy-handed approach where it turned off all available clocks, while also possibly setting bits which are not documented in the R-Car datasheet. Update the tables so that only the bits which are documented are set or cleared when tearing down the clock driver. Note that the only clock left running before booting Linux are now MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2021-04-23clk: Fix typo in Zynq Kconfig symbol descriptionMichal Simek1-1/+1
Trivial typo fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-04-19clk: meson-g12a: add PCIe gatesNeil Armstrong1-0/+2
Add missing gates used for PCIe. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-16clk: sunxi: h6: Add XHCI clocksSamuel Holland1-0/+2
The XHCI controller has its own clock and reset. Add them. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-16clk: sunxi: Add a dummy clock driver for the RTCSamuel Holland2-0/+37
The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is used, among other things, by the XHCI controller in the H6. To be able to call clk_get_bulk() on the XHCI controller, some device needs to provide all referenced clocks. Since LOSC is a fixed-rate always-on clock, implementation is trivial. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-08clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flagBin Meng1-0/+1
This driver is needed in the pre-relocation phase as the serial driver depends on it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2021-04-06clk: Return -ENOSYS when system call is not availableSimon Glass1-4/+4
Update clk_composite_set_parent() to use -ENOSYS, which is the correct error code for U-Boot. Also rearrange the code so that the error condition is clearly indicated and the function runs to the end in the normal case, since this is the common style in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-04-06clk: Update drivers to use -EINVALSimon Glass9-17/+17
At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-31Merge tag 'xilinx-for-v2021.07' of ↵Tom Rini1-81/+170
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.07 net: - Fix gem PCS support spi: - Small trivial fixes zynq: - Enable time/timer commands - Update bitmain platform - Several DT changes zynqmp: - Update clock driver - mini config alignments - Add/update psu_init for zcu208/zcu216/zc1275 - Several DT changes - Enable efi debug command (also for Versal)
2021-03-30clk: zynqmp: Fix clk dump valuesT Karthik Reddy1-81/+170
With "clk dump" command, few clocks are showing up incorrect values and some clocks are displayed as "unknown". Add missing clocks to zynqmp clock driver to display proper clocks rates. Implement a simple way to get clock source, instead of calling functions. Change existing functions to this simple mechanism. Fix gem clock name "gem_rx" to "gem_tx" which was incorrect. Change dbf_fpd & dbf_lpd clk names to dbg_fpd & dbg_lpd. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
2021-03-26dm: Rename device_get_by_driver_info_idx()Simon Glass1-1/+1
This function finds a device by its driver_info index. With of-platdata-inst we do not use driver_info, but instead instantiate udevice records at build-time. However the semantics of using the function are the same in each case: the caller provides an index and gets back a device. So rename the function to device_get_by_ofplat_idx(), so that it can be used for both situations. The caller does not really need to worry about the details. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26clk: sandbox: Create a special fixed-rate driverSimon Glass1-0/+33
Create a version of this driver for sandbox so that it can use the of-platdata struct. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26clk: fixed-rate: Export driver parts for OF_PLATDATA_INSTSimon Glass1-4/+10
We need to allow SoCs to create their own drivers for this so that they can use their own of-platdata structs. To minimise code duplication, export the driver operations and the ofdata_to_plat() setup function. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26clk: sandbox: Move priv/plat data to a header fileSimon Glass2-13/+0
At present the structs used by this driver are not accessible outside it, so cannot be used with OF_PLATDATA_INST. Move them to a header file to fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-11clk: stm32mp1: gets root clocks from fdtEtienne Carriere1-39/+23
This change makes stm32mp1 clock driver to get the root clocks reference from the device node in the FDT rather than fetching straight these clocks by their name. Driver now stores the clock reference and use it to know if a root clock is present, get its rate or gets its related udevice reference. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-02-23Merge tag 'xilinx-for-v2021.04-rc3' of ↵Tom Rini3-0/+70
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
2021-02-23clk: versal: Add support to enable clocksT Karthik Reddy1-0/+11
Add clock enable functionality in versal clock driver to enable clocks from peripheral drivers using clk_ops. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23clk: zynqmp: Add support to enable clocksT Karthik Reddy1-0/+49
Add clock enable functionality in zynqmp clock driver to enable clocks from peripheral drivers using clk_ops. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23clk: zynq: Add dummy clock enable functionMichal Simek1-0/+10
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-22clk: ti: improve debug messages for clkctrl driverDario Binacchi1-2/+2
The previous version printed the same debug message for both the enable and disable routines without highlighting whether you were enabling or disabling the module. It is now clear whether you are enabling or disabling the module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-02-15Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini20-2/+20
- Merge the patch to take <asm/global_data.h> out of <common.h>
2021-02-11clk: at91: compat: partially revert "dm: Remove uses of device_bind_offset()"Eugen Hristev1-8/+12
Revert changes in at91 compat.c that cause u-boot to fail booting on sama5d4_xplained and sama5d2_xplained Log below: <debug_uart> No serial driver found Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Could not initialize timer (err -19) Fixes: a2703ce10c ("dm: Remove uses of device_bind_offset()") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-09clk: stm32mp1: add support of I2C6_KPatrick Delaunay1-0/+1
Add support of missing I2C6_K with bit 3 of RCC_MC_APB5ENSETR = I2C6EN: I2C6 peripheral clocks enable. This patch allows customer to use I2C6 in SPL or in U-Boot as other I2C instance, already support in clk driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass20-2/+20
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-31clk: x86: Correct the driver nameSimon Glass1-2/+2
The current driver name does not match its compatible string, so of-platdata does not work correctly. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31clk: Add debugging for return valuesSimon Glass1-5/+11
Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-26Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini3-0/+128
- New Allwinner H616 SoC support (sans Ethernet & USB) - H6 DT update - Tanix TX6 TV box support - OrangePi 3 support - OrangePi Zero2 (H616) support
2021-01-26clk: sunxi: Add support for H616 clocksJernej Skrabec3-0/+128
This commit introduces DM H616 clock driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25Merge tag 'mips-pull-2021-01-24' of ↵Tom Rini2-0/+160
https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: add support for Mediatek MT7620 SoCs
2021-01-24clk: add clock driver for MediaTek MT7620 SoCWeijie Gao2-0/+160
This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-23clk: imx: Add ECSPI to iMX8MNMarek Vasut1-0/+29
Add ECSPI clock entries to iMX8MN clock driver. Only make those entries available in case SPI support in U-Boot is enabled at all to conserve space, esp. in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2021-01-18clk: aspeed: Add AST2600 clock supportRyan Chen2-0/+1174
This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2021-01-18clk: mediatek: Add MT8183 clock driverFabien Parent2-0/+824
Add the topckgen, apmixedsys and infracfg clock driver for the MT8183 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18clk: Add Microchip PolarFire SoC clock driverPadmarao Begari8-0/+514
Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-15dm: fix build errors generated by last mergesDario Binacchi5-5/+5
Something was wrong in the merge process into the mainline. Some added patches access driver structure fields and functions that have been modified by previous patches. The patch renames: - dev_get_platdata to dev_get_plat - dev_get_uclass_platdata to dev_get_uclass_plat - ofdata_to_platdata to of_to_plat - plat_data_alloc_size to plat_auto - priv_auto_alloc_size to priv_auto - video_uc_platdata to video_uc_plat Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-13Merge tag 'u-boot-stm32-20210113' of ↵Tom Rini3-127/+129
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Enable logging features for stm32mp15 boards - Update MAINTAINERS emails for STI and STM32 - Activate OF_LIVE for ST stm32mp15 boards - Switch to MCO2 for PHY 50 MHz clock for DHCOM boards - Correction in stm32prog command on uart: always flush DFU on start command - Update USB-C power detection algorithm on DK boards
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