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path: root/drivers/clk
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2021-07-27clk: stm32mp1: add support of missing SPI clocksPatrick Delaunay1-0/+13
Add the missing SPI clock even if these instances are not available on STMicroelectronics boards: SPI2_K, SPI3_K, SPI4_K, SPI6_K. With this patch, the SPI2 / SPI3 / SPI4 / SPI6 instances can be used on customer design without the clock driver error: stm32mp1_clk_get_id: clk id 131 not found Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-26clk: zynqmp: Add support for enabling clock on lpd_lsbusMichal Simek1-0/+1
lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis, spis, ttcs, uarts, watchdog that's why make sense to also enable access to change this clock. For this clock you already get the rate. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵Tom Rini1-1/+22
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-16Merge branch '2021-07-15-assorted-fixes'Tom Rini1-1/+5
- Large number of Coverity reported issues addressed - m41t62 bugfix - Support more Android image compression formats - FIT + DTO bugfix
2021-07-16clk: stm32mp1: add support of SYSCFG clockPatrick Delaunay1-0/+1
Add the support of SYSCFG clock used by syscon driver to prepare the clock management of STM32MP_SYSCON_SYSCFG. This clock is already defined in kernel device tree, stm32mp151.dtsi but not yet supported in the syscon driver: syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; clocks = <&rcc SYSCFG>; }; It is safe to support this clock in U-Boot driver with RCC_MC_APB3ENSETR, Bit 11 SYSCFGEN: SYSCFG peripheral clocks enable. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16clk: Detect failure to set defaultsSimon Glass1-1/+5
When the default clocks cannot be set, the clock is silently probed and the error is ignored. This is incorrect, since having the clocks at the correct speed may be important for operation of the system. Fix it by checking the return code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-14clk: uniphier: Add PCIe clock entryKunihiko Hayashi1-0/+3
Add clock control for PCIe controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-10clk: imx8mm: Add SPI clocksFrieder Schrempf1-1/+22
Add the clocks for the ECSPI controllers. This is ported from Linux v5.13-rc4. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-07-08clk: armada-37xx: Set DM_FLAG_PRE_RELOCMarek Behún2-0/+2
Setting DM_FLAG_PRE_RELOC for Armada 3720 clock drivers (TBG and peripheral clocks) makes it possible for serial driver to retrieve clock rates via clk API. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-07Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmTom Rini1-0/+2
various minor sandbox improvements
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan1-3/+3
Replace 'pciaux' with 'pcieaux', including name string and function prefix. The old name string, 'pciaux', might cause an error if PCIe driver is changed to use clk_get_by_name() with 'pcieaux' to get clock. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-01Merge tag 'xilinx-for-v2021.10' of ↵Tom Rini3-0/+198
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.10 clk: - Add driver for Xilinx Clocking Wizard IP fdt: - Also record architecture in /fit-images net: - Fix plat/priv data handling in axi emac - Add support for 10G/25G speeds pca953x: - Add missing dependency on i2c serial: - Fix dependencies for DEBUG uart for pl010/pl011 - Add setconfig option for cadence serial driver watchdog: - Add cadence wdt expire now function zynq: - Update DT bindings to reflect the latest state and descriptions zynqmp: - Update DT bindings to reflect the latest state and descriptions - SPL: Add support for ECC DRAM initialization - Fix R5 core 1 handling logic - Enable firmware driver for mini configurations - Enable secure boot, regulators, wdt - Add support xck devices and 67dr - Add psu init for sm/smk-k26 SOMs - Add handling for MMC seq number via mmc_get_env_dev() - Handle reserved memory locations - Add support for u-boot.itb generation for secure OS - Handle BL32 handoffs for secure OS - Add support for 64bit addresses for u-boot.its generation - Change eeprom handling via nvmem aliases
2021-06-29Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh ↵Tom Rini7-0/+371
into next - V3U Falcon board support
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini1-2/+6
Prepare v2021.07-rc5 # gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # configs/am64x_evm_r5_defconfig
2021-06-24clk: renesas: Add R8A779A0 clock tablesHai Pham7-0/+338
Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot
2021-06-24clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock codeMarek Vasut2-0/+33
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value from cpg_pll_configs table while PLL{20,21,30,31,4} use different control offset. Introduce new types to handle this and handle those types in the Gen3 clock code. Based on "clk: renesas: Add support for R8A779A0 V3U PLLn" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-23clk: zynq: Add clock wizard driverZhengxun3-0/+198
The Clocking Wizard IP supports clock circuits customized to your clocking requirements. The wizard support for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle. Limited by U-Boot clk uclass without set_phase API, this patch only provides set_rate to modify the frequency. Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-19Merge tag 'u-boot-rockchip-20210618' of ↵Tom Rini2-0/+2960
https://source.denx.de/u-boot/custodians/u-boot-rockchip into next - New SoC platform support: rk3568; - rockchip pcie Code compile issue fix; - Board fix for rk3399 Khadas Edge; - Add Rockchip NFC driver;
2021-06-18clk: cosmetic change in uclassPatrick Delaunay1-1/+1
Remove the tab in clk_get_bulk to respect the coding rules. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18rockchip: rk3568: add clock driverElaine Zhang2-0/+2960
Add rk3568 clock driver and cru structure definition. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-17clk: k210: Move k210 clock out of its own subdirectorySean Anderson5-15/+14
Now that we have only one clock driver, we don't need to have our own subdirectory. Move the driver back with the rest of the clock drivers. The MAINTAINERS for kendryte pinctrl is also fixed since it has always been wrong. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Remove bypass driverSean Anderson2-274/+1
This driver no longer serves a purpose now that we have moved away from CCF. Drop it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Don't set PLL rates if we are already at the correct rateSean Anderson1-7/+8
This speeds up boot by preventing multiple reconfigurations of the PLLs. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Re-add support for setting rateSean Anderson1-5/+84
This adds support for setting clock rates, which was left out of the initial CCF expunging. There are several tricky bits here, mostly related to the PLLS: * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks will be stopped. * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent stopping the CPU while we configure PLL0's rate, ACLK is reparented to IN0 while PLL0 is disabled. * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented, so we instead just disallow changing PLL1's rate after relocation (when we are using the AISRAM). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Implement soc_clk_dumpSean Anderson1-2/+66
Since we are no longer using CCF we cannot use the default soc_clk_dump. Instead, implement our own. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Move pll into the rest of the driverSean Anderson3-594/+601
Now that there no separate PLL driver, we can no longer make the PLL functions static. By moving the PLL driver in with the rest of the clock code, we can make these functions static again. We still keep the pll header for unit testing, but it is pretty reduced. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Rewrite to remove CCFSean Anderson3-523/+439
This is effectively a complete rewrite to remove all dependency on CCF. The code is now smaller, and so is the binary. It also takes up less memory at runtime (since we don't have to create 40 udevices). In general, I am much happier with this driver as much of the complexity and late binding has been removed. The k210_*_params structs which were previously used to initialize CCF clocks are now used as the complete configuration. Since we can write our own division logic, we can now do away with several "half" clocks which only existed to provide constant factors of two. The clock IDs have been renumbered to remove unused clocks. This may not be the last time they are renumbered, since we have diverged with Linux. There are also still a few clocks left out which may need to be added back in. In general, I have tried to leave out behavioral changes. However, there is a small bugfix regarding ACLK. According to the technical reference manual, its mux comes *after* its divider (which is present only for PLL0). This would have required yet another intermediate clock to fix with CCF, but with the new driver it is just 2 lines of code :) Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: Allow force setting clock defaults before relocationSean Anderson2-11/+18
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11clk: add support for TI K3 SoC clocksTero Kristo3-0/+387
Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: add support for TI K3 SoC PLLTero Kristo3-0/+296
Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: fix set_rate to clean up cached rates for the hierarchyTero Kristo1-0/+19
Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: fix assigned-clocks to pass with deferring providerTero Kristo1-0/+18
If a clock provider is not ready for assigning default rates/parents during its probe, it may return -EPROBE_DEFER directly from xlate. Handle this special case properly by skipping the entry and adjusting the return value to pass. The defaults will be handled properly in post probe phase then. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: sci-clk: fix return value of set_rateTero Kristo1-2/+4
Set rate should return the new clock rate on success, and negative error value on failure. Fix this, as currently set_rate returns 0 on success. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: do not attempt to fetch clock pointer with null deviceTero Kristo1-0/+2
Bail out early if device returned for the parent clock is null. This avoids warning prints like this when doing clk dump: dev_get_uclass_priv: null device Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: fixed_rate: add API for directly registering fixed rate clocksTero Kristo1-0/+45
Current driver only supports registering fixed rate clocks from DT. Add new API which makes it possible to register fixed rate clocks directly from e.g. platform specific clock drivers. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-09clk: imx: clk-imxrt1050: introduce IMXRT1050_CLK_USBOH3Giulio Benetti1-0/+2
Usb needs IMXRT1050_CLK_USBOH3 clock to be enabled, so let's add it to clock driver. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APBGiulio Benetti1-2/+4
Lcd peripheral needs 2 different gates to be enable to work, so let's introduce the missing one(LCDIF_PIX) and rename the existing one (LCDIF_APB). Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-05-31drivers: clk: add fu740 supportGreen Wan8-753/+1286
Add fu740 support. One abstract layer is added for supporting multiple chips such as fu540 and fu740. Signed-off-by: Green Wan <green.wan@sifive.com>
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún1-2/+2
This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-21clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handlingMarek Vasut1-43/+43
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Add register pointers into struct cpg_mssr_infoHai Pham3-45/+65
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Introduce enum clk_reg_layoutHai Pham1-0/+6
From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()Hai Pham4-6/+8
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Make reset controller modemr register offset configurableMarek Vasut20-5/+21
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Add support for RPCD2 clockHai Pham2-5/+17
This supports RPCD2 clock handling. While at it, add the check point for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd number Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Fix Realtime Module Stop Control Register offsetsHai Pham1-1/+1
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual. The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change doesn't affect it. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Fix incorrect return RPC clk_get_rateHai Pham1-1/+1
RPC clk_get_rate will return error code instead of expected clock rate. Fix this. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Reinstate RPC clock on R-Car D3/E3Marek Vasut2-0/+18
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization. The D3 and E3 clock drivers do not contain RPC clock entries mainline Linux yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12Marek Vasut7-163/+212
Synchronize R-Car Gen3 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-15 16:45:19 +0300