starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-03-23	arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dump	Vipul Kumar	1	-0/+75
2018-03-23	clk: zynq: Show watchdog clock rate properly	Michal Simek	1	-1/+1
2018-03-19	clk: stm32mp1: add clock tree initialization	Patrick Delaunay	1	-0/+576
2018-03-19	clk: add driver for stm32mp1	Patrick Delaunay	3	-0/+1166
2018-03-16	clk: at91: clk-system: add set/get_rate operations	Wenyou Yang	1	-0/+26
2018-03-16	clk: at91: add PLLADIV driver	Wenyou Yang	2	-1/+89
2018-03-16	clk: at91: add USB Host clock driver	Wenyou Yang	3	-0/+155
2018-03-14	clk: clk_stm32f: Add DSI clock support	Patrice Chotard	1	-1/+1
2018-03-14	clk: clk_stm32f: Add set_rate for LTDC clock	Patrice Chotard	1	-0/+100
2018-03-14	clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock	Patrice Chotard	1	-1/+36
2018-03-14	clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() part	Patrice Chotard	1	-31/+74
2018-03-14	clk: clk_stm32f: No more need of 48Mhz from PLL_SAI	Patrice Chotard	1	-21/+8
2018-03-14	clk: clk_stm32f: Fix RCC_PLLSAICFGR mask defines	Patrice Chotard	1	-4/+4
2018-03-14	clk: clk_stm32f: Fix stm32_clk_get_rate()	Patrice Chotard	1	-5/+7
2018-03-14	board: stm32: switch to DM STM32 timer	Patrice Chotard	1	-15/+0
2018-03-14	clk: clk_stm32h7: Fix prescaler for Domain 3	Patrice Chotard	1	-3/+4
2018-03-14	clk: clk_stm32h7: Fix stm32_clk_get_rate() for timer	Patrice Chotard	1	-12/+90
2018-03-14	clk: clk_stm32f: Fix stm32_clk_get_rate() for timer	Patrice Chotard	1	-17/+99
2018-03-13	rockchip: clk: rk1108: convert to use live dt	Kever Yang	1	-1/+1
2018-03-13	rockchip: clk: rk3328: convert to use live dt	Kever Yang	1	-1/+1
2018-03-13	rockchip: clk: rk3288: convert to use live dt	Kever Yang	1	-1/+1
2018-03-13	rockchip: clk: rk322x: convert to use live dt	Kever Yang	1	-1/+1
2018-03-13	rockchip: clk: rk3188: convert to use live dt	Kever Yang	1	-1/+1
2018-03-13	rockchip: clk: rk3036: convert to use live dt	Kever Yang	1	-1/+1
2018-03-05	clk: renesas: Add R8A77965 M3N entries	Marek Vasut	1	-0/+19
2018-02-24	rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL	Philipp Tomsich	1	-0/+9
2018-02-24	rockchip: clk: rk3368: handle clk_enable requests for GMAC	Philipp Tomsich	1	-0/+19
2018-02-24	rockchip: clk: rk3399: handle clk_enable requests for GMAC	Philipp Tomsich	1	-0/+10
2018-02-16	clk: rmobile: Assure SD-IF clock are configured correctly	Marek Vasut	1	-0/+2
2018-01-29	clk: clk_stm32: Add .set_rate callback	Patrice Chotard	1	-0/+6
2018-01-28	Merge git://git.denx.de/u-boot-rockchip	Tom Rini	6	-19/+701
2018-01-28	rockchip: clk: guard set_parent implementations against OF_PLATDATA	Philipp Tomsich	3	-6/+12
2018-01-28	clk: rockchip: clk_rk3368: Implement "assign-clock-parent"	David Wu	1	-7/+84
2018-01-28	clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-...	David Wu	1	-8/+98
2018-01-28	clk: rockchip: Add rk322x gamc clock support	David Wu	1	-0/+107
2018-01-28	clk: rockchip: Add rk3328 gamc clock support	David Wu	1	-0/+178
2018-01-28	rockchip: clk: rk3399: accept all assigned-clocks from the 'cru'-node	Philipp Tomsich	1	-0/+18
2018-01-28	clk: implement clk_set_defaults()	Philipp Tomsich	1	-0/+118
2018-01-28	rockchip: clk: rk3399: implement set_parent() operation	Philipp Tomsich	1	-2/+72
2018-01-28	clk: refactor clk_get_by_index() into clk_get_by_indexed_prop()	Philipp Tomsich	1	-2/+8
2018-01-28	clk: add clk_set_parent()	Philipp Tomsich	1	-0/+12
2018-01-28	clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value	Patrice Chotard	1	-1/+1
2018-01-28	clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks()	Patrice Chotard	1	-6/+6
2018-01-28	clk: clk_stm32f: Remove STMMAC clock setup	Patrice Chotard	1	-6/+0
2018-01-28	clk: stm32: retrieve external oscillator frequency from DT	Patrice Chotard	1	-21/+57
2018-01-28	Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh	Tom Rini	16	-1104/+3094
2018-01-26	Merge git://git.denx.de/u-boot-spi	Tom Rini	2	-8/+8
2018-01-25	clk: renesas: Import R8A7794 E2 clock tables	Marek Vasut	3	-0/+284
2018-01-25	clk: renesas: Import R8A7792 V2H clock tables	Marek Vasut	3	-0/+257
2018-01-25	clk: renesas: Import R8A7791/R8A7793 M2 clock tables	Marek Vasut	3	-0/+308