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path: root/drivers/clk
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2018-03-23arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dumpVipul Kumar1-0/+75
This patch print pl clocks (pl0...pl3) and watchdog clock using clk dump. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23clk: zynq: Show watchdog clock rate properlyMichal Simek1-1/+1
watchdog clock is also connected to cpu 1X clocksource. Zynq> clk dump ... Before: swdt 4294967290 After: swdt 111111110 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-19clk: stm32mp1: add clock tree initializationPatrick Delaunay1-0/+576
add binding and code for clock tree initialization from device tree Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19clk: add driver for stm32mp1Patrick Delaunay3-0/+1166
add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-16clk: at91: clk-system: add set/get_rate operationsWenyou Yang1-0/+26
To support set/get the clock rate, add set/get_rate operations. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2018-03-16clk: at91: add PLLADIV driverWenyou Yang2-1/+89
As said in the SAMA5D2 datasheet, the PLLA clock must be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2018-03-16clk: at91: add USB Host clock driverWenyou Yang3-0/+155
Add USB clock driver to configure the input clock and the divider in the PMC_USB register to generate a 48MHz and a 12MHz signal to the USB Host OHCI. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2018-03-14clk: clk_stm32f: Add DSI clock supportPatrice Chotard1-1/+1
DSI clock is available on STM32F769-disco and STM32F469-disco board. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32f: Add set_rate for LTDC clockPatrice Chotard1-0/+100
Implement set_rate() for LTDC clock only, set_rate for other clocks will be added if needed. This is needed by future LTDC driver improvements. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clockPatrice Chotard1-1/+36
Configure SAI PLL configuration to generate LTDC pixel clock on the PLLSAIR output. PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() partPatrice Chotard1-31/+74
Rework the way SDMMC clock get rate is done in a more generic way : _ Add stm32_clk_get_pllsai_rate() which give the PLLSAI indicated output rate. _ Add stm32_clk_get_pllsai_vco_rate() which give the VCO internal rate. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32f: No more need of 48Mhz from PLL_SAIPatrice Chotard1-21/+8
Initially, 48Mhz for SDIO clock was generated from SAI pll for STM32F469 and STM32F746 SoCs, but this solution was not suitable for STM32F429 SoCs. A generic solution is to used the PLL_Q output as 48Mhz clock for all STM32F SOCs family. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32f: Fix RCC_PLLSAICFGR mask definesPatrice Chotard1-4/+4
Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32f: Fix stm32_clk_get_rate()Patrice Chotard1-5/+7
Wrong parameter was passed to stm32_clk_pll48clk_rate(). sysclk (PLL_p output value) was passed instead of VCO value. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14board: stm32: switch to DM STM32 timerPatrice Chotard1-15/+0
Use available DM stm32_timer driver instead of dedicated mach-stm32/stm32fx/timer.c. Remove all defines or files previously used for timer usage in arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx Enable DM STM32_TIMER for STM32F4/F7 and H7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32h7: Fix prescaler for Domain 3Patrice Chotard1-3/+4
d1cfgr register was used to calculate the domain 3 prescaler value instead of d3cfgr. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32h7: Fix stm32_clk_get_rate() for timerPatrice Chotard1-12/+90
For timer clock, an additional prescaler is used which was not taken into account previously. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-14clk: clk_stm32f: Fix stm32_clk_get_rate() for timerPatrice Chotard1-17/+99
For timer clock, an additionnal prescaler is used which was not taken into account previously. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13rockchip: clk: rk1108: convert to use live dtKever Yang1-1/+1
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3328: convert to use live dtKever Yang1-1/+1
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3288: convert to use live dtKever Yang1-1/+1
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk322x: convert to use live dtKever Yang1-1/+1
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3188: convert to use live dtKever Yang1-1/+1
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13rockchip: clk: rk3036: convert to use live dtKever Yang1-1/+1
Use live dt api to get cru base addr. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-05clk: renesas: Add R8A77965 M3N entriesMarek Vasut1-0/+19
Add entries for the R8A77965 M3N SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-02-24rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLLPhilipp Tomsich1-0/+9
The device-tree node for the PMU clk controller assigns to its parent (i.e. PLL_PPLL) even though this clock currently is set up statically by an init-function. In order to avoid unexpected failures, a simple implementation of set_rate (which accepts requests, but notifies the caller of the preset frequency in its return value) and get_rate (which always returns the preset frequency) are added. Note that this is required for the RK808 PMIC to probe successfully on the RK3399-Q7, following the support for the assigned-clocks property. References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-02-24rockchip: clk: rk3368: handle clk_enable requests for GMACPhilipp Tomsich1-0/+19
Since commit ba1f96672522 ("net: designware: add clock support"), the designware GMAC driver enables all referenced clocks. While this is a no-op for the RK3368 during boot-up (reset behaviour has all the clock gates open anyway), we still need to handle the clock-ids passed in the enable op of the clock-driver and return a success. This change extends the RK3368 clk driver to: (a) provide a enable op (b) signals success to the caller when the clocks for the GMAC are enabled (no actual action is necessary as the gates are open after reset) References: commit ba1f96672522 ("net: designware: add clock support") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-02-24rockchip: clk: rk3399: handle clk_enable requests for GMACPhilipp Tomsich1-0/+10
Since commit ba1f96672522 ("net: designware: add clock support"), the designware GMAC driver enables all referenced clocks. While this is a no-op for the RK3399 during boot-up (reset behaviour has all the clock gates open anyway), we still need to handle the clock-ids passed in the enable op of the clock-driver and return a success. This change extends the enable-op of the rk3399 clk driver to signal success to the caller when the clocks for the GMAC are enabled. References: commit ba1f96672522 ("net: designware: add clock support") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-02-16clk: rmobile: Assure SD-IF clock are configured correctlyMarek Vasut1-0/+2
The SD driver calls clk_set_rate() before clk_enable(), yet clk_set_rate() implementation in the clock driver does not set the SD-IF divider. Fix it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-29clk: clk_stm32: Add .set_rate callbackPatrice Chotard1-0/+6
Since 'commit f4fcba5c5baa ("clk: implement clk_set_defaults()")' STM32F4 family board can't boot. Above patch calls clk_set_rate() for all nodes with assigned-clock-rates property. Clock driver for STM32F family doesn't implement .set_rate callback which make clk_set_defaults() exit on error and prevent board to boot. Fixes: f4fcba5c5baa ("clk: implement clk_set_defaults()") Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-28Merge git://git.denx.de/u-boot-rockchipTom Rini6-19/+701
2018-01-28rockchip: clk: guard set_parent implementations against OF_PLATDATAPhilipp Tomsich3-6/+12
The set_parent implementations do not make sense when OF_PLATDATA is enabled. We guard these against OF_PLATDATA and don't populate the set_parent-op when this is the case. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: clk_rk3368: Implement "assign-clock-parent"David Wu1-7/+84
Implement the setting parent for gmac clock, and add internal pll div set for mac clk. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and ↵David Wu1-8/+98
"assign-clock-rate" The RK3288 CRU-node assigns rates to a number of clocks that are not implemented in the RK3288 clock-driver (but which have been sufficiently initialised from rkclk_init()): for these clocks, we implement the gmac clock set parent, but simply ignore the others' set_rate() operation and return 0 to signal success. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: Add rk322x gamc clock supportDavid Wu1-0/+107
Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28clk: rockchip: Add rk3328 gamc clock supportDavid Wu1-0/+178
The rk3328 soc has two gmac controllers, one is gmac2io, the other is gmac2phy. We use the gmac2io rgmii interface for 1000M phy here. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-28rockchip: clk: rk3399: accept all assigned-clocks from the 'cru'-nodePhilipp Tomsich1-0/+18
The RK3399 CRU-node assigns rates to a number of clocks that are not implemented in the RK3399 clock-driver (but which have been sufficiently initialised from rkclk_init()): for these clocks, we simply ignore the set_rate() operation and return 0 to signal success. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28clk: implement clk_set_defaults()Philipp Tomsich1-0/+118
Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-28rockchip: clk: rk3399: implement set_parent() operationPhilipp Tomsich1-2/+72
This implements the (newly added) set_parent() operation for the RK3399 with a focus on allowing the RGMII clock parent to be configured via the assigned-clock-parents property of the GMAC node. This implementation supports only the GMAC (in fact only the RGMII clock parent) and allows to set this clock's parent either to the internal SCLK_GMAC or to an external clock input (identifiable by it providing a 'clock-output-name' of "gmac_clkin"). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28clk: refactor clk_get_by_index() into clk_get_by_indexed_prop()Philipp Tomsich1-2/+8
The logic in clk_get_by_index() may be useful for other properties than 'clocks': e.g. 'assigned-clocks' and 'assigned-clock-parents' follows the same model. This commit refactors clk_get_by_index() by introducing an internal function clk_get_by_indexed_prop() that allows to specify the name of the property to process. The original clk_get_by_index() call is simply directed through this helper function with the property name fixed to "clocks". Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28clk: add clk_set_parent()Philipp Tomsich1-0/+12
Clocks may support multiple parents: this change introduces an optional operation on the clk-uclass to set a clock's parent. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-28clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider valuePatrice Chotard1-1/+1
PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR register, available combination are : 00: PLLSAIP = 2 01: PLLSAIP = 4 10: PLLSAIP = 6 11: PLLSAIP = 8 Previously, the divider value was incorrectly set to 6. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-28clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks()Patrice Chotard1-6/+6
Move SYSCFG clock setup into configure_clocks() instead of calling clock_setup() from board file. As this clock is only needed in case of ethernet enabled and as both stm32f4 and stm32f7 are using the Designware ethernet IP, we use CONFIG_ETH_DESIGNWARE to only enable this clock if needed. Move the RMII setup from board_early_init_f() to board_init() to insure that RMII bit is set only when clock driver is initialized. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-28clk: clk_stm32f: Remove STMMAC clock setupPatrice Chotard1-6/+0
Thanks to 'commit ba1f96672522 ("net: designware: add clock support")' we don't need anymore to setup the STMMAC clock in board. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-01-28clk: stm32: retrieve external oscillator frequency from DTPatrice Chotard1-21/+57
All current STM32F4 supported boards uses a 8MHz external oscillator. All current STM32F7 supported boards uses a 25MHz external oscillator. In order to introduce the new stm32f429-evaluation board which uses a 25MHz external oscillator without creating a dedicated struct stm32_clk_info for this board, retrieve the external oscillator frequency from DT and set pll_m accordingly to obtain 1MHz for the VCO. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-28Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini16-1104/+3094
2018-01-26Merge git://git.denx.de/u-boot-spiTom Rini2-8/+8
2018-01-25clk: renesas: Import R8A7794 E2 clock tablesMarek Vasut3-0/+284
Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-25clk: renesas: Import R8A7792 V2H clock tablesMarek Vasut3-0/+257
Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-25clk: renesas: Import R8A7791/R8A7793 M2 clock tablesMarek Vasut3-0/+308
Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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