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path: root/drivers/clk
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2023-02-02clk: renesas: Switch to new SD clock handlingHai Pham2-91/+112
2023-02-02clk: renesas: Handle E3/D3 RPCSRC clockHai Pham1-0/+31
2023-02-02clk: renesas: Introduce and use rcar_clk_get_rate64_div_table functionHai Pham2-34/+64
2023-02-02clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct clk_div_t...Marek Vasut2-11/+3
2023-02-02clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_regMarek Vasut1-14/+13
2023-02-02clk: renesas: Use pre-defined offset for RPC clocksHai Pham2-4/+1
2023-02-02clk: renesas: Add and enable CPG reset driverMarek Vasut14-112/+153
2023-02-02clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportHai Pham3-0/+26
2023-02-02clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960Hai Pham2-4/+4
2023-02-02clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7Marek Vasut1-10/+13
2023-02-02clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7Marek Vasut1-11/+12
2023-02-02clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7Marek Vasut1-11/+14
2023-02-02clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7Marek Vasut1-15/+17
2023-02-02clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7Marek Vasut3-31/+77
2023-02-02clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.1.7Marek Vasut2-8/+14
2023-02-02clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.1.7Marek Vasut1-10/+13
2023-02-02clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.1.7Marek Vasut1-6/+7
2023-02-02clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.1.7Marek Vasut1-9/+15
2023-02-02clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with ...Marek Vasut1-16/+17
2023-02-02clk: renesas: Synchronize R8A7795 H3 clock tables with Linux 6.1.7Marek Vasut1-9/+19
2023-02-02clk: renesas: Add dummy SDnH clockHai Pham2-0/+7
2023-02-02ARM: dts: rmobile: Synchronize DTs with Linux 6.1.7Marek Vasut1-1/+1
2023-01-27Merge tag 'xilinx-for-v2023.04-rc1' of https://source.denx.de/u-boot/custodia...Tom Rini1-1/+3
2023-01-23clk: sunxi: Add DE2 display-related clocks/resetsSamuel Holland7-0/+141
2023-01-16clk: versal: Return error in case if clock setup failedJay Buddhabhatti1-1/+3
2023-01-16clk: rockchip: Add rv1126 clk supportJagan Teki2-0/+1890
2023-01-16rockchip: clk: add watchdog clock to px30_clk_enableQuentin Schulz1-0/+3
2022-12-21Merge tag 'v2023.01-rc4' into nextTom Rini7-4/+1694
2022-12-19rockchip: rk3128-cru: sync the clock dt-binding header from LinuxJohan Jonker1-4/+4
2022-12-09arm: mach-k3: am62a: introduce auto-generated SoC dataBryan Brattlof1-0/+6
2022-12-07clk: stm32mp13: introduce STM32MP13 RCC driverGabriel Fernandez6-0/+1690
2022-12-06global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini1-1/+1
2022-11-15clk: microchip: mpfs: fix criticality of peripheral clocksConor Dooley1-7/+21
2022-11-15clk: microchip: mpfs: fix periph clk parentageConor Dooley3-38/+42
2022-11-15clk: microchip: mpfs: fix reference clock handlingConor Dooley3-1/+149
2022-11-15clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()Conor Dooley5-35/+20
2022-10-24Merge tag 'u-boot-imx-20221024' of https://gitlab.denx.de/u-boot/custodians/u...Tom Rini1-37/+49
2022-10-21clk-imx8mm: Only build QSPI clocks when CONFIG_NXP_FSPI=yFabio Estevam1-4/+9
2022-10-21clk-imx8mm: Only build ecspi clocks when CONFIG_DM_SPI=yFabio Estevam1-13/+18
2022-10-21clk-imx8mm: Move CLK_ENET_AXI to the non-SPL sectionFabio Estevam1-4/+4
2022-10-21clk-imx8mm: Only build PWM clocks in non-SPL codeFabio Estevam1-16/+18
2022-10-21Merge tag 'u-boot-rockchip-20221020' of https://source.denx.de/u-boot/custodi...Tom Rini1-1/+1
2022-10-20Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini1-1/+1
2022-10-20Merge tag 'clk-2023.01' of https://source.denx.de/u-boot/custodians/u-boot-clkTom Rini2-5/+21
2022-10-20k210: fix k210_pll_calc_config()Heinrich Schuchardt1-1/+1
2022-10-19clk: update clk_clean_rate_cache to use private clk structPatrick Delaunay1-1/+17
2022-10-19rockchip: clk: pll: Fix constant typoMichal Suchanek1-3/+3
2022-10-19clk: change return type of clk_get_parent_rate from long long to ulongMichal Suchanek1-1/+1
2022-10-19arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented rangeXavier Drudis Ferran1-1/+1
2022-10-11Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custo...Tom Rini1-1/+1