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path: root/drivers/clk
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2023-05-09clk: rockchip: correct trivial typo in debug messageEugen Hristev13-16/+16
s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06drivers: fix debug string with fdt_addr_t inputJohan Jonker1-4/+5
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so fix some debug strings with fdt_addr_t to be able to handle both sizes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use devfdt_get_addr_ptr when cast to pointerJohan Jonker2-2/+2
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_ptr instead of the devfdt_get_addr function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use devfdt_get_addr_index_ptr when cast to pointerJohan Jonker1-2/+2
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-01Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini11-0/+43
Please pull the second part of the sunxi pull request for this cycle. Another bunch of patches that replace old-school U-Boot hacks with proper DM based code, this time for the raw NAND flash driver, and the USB PHY VBUS detection code. Plus two smaller patches that were sitting in my inbox for a while. Gitlab CI passed. In lack of some supported board with NAND flash I couldn't really test this part, but apparently this was tested by the reviewer. I briefly ran the branch on some boards with USB-OTG, and this still worked.
2023-04-29Merge branch 'for-2023.07' of ↵Tom Rini1-0/+7
https://source.denx.de/u-boot/custodians/u-boot-mpc8xx This pull request adds support for the last CPU board from CS GROUP France (previously CSSI). That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence its name) and can be plugged in place of the CMPC885 board. In order to support that new board, the following changes are included in this series: - Make the mpc8xx watchdog driver more generic for reusing it with mpc83xx - Fix various small problems on mpc83xx platform - Add a GPIO Driver for QE GPIOs - Add support for mpc832x into mpc83xx SPI driver - Refactor existing board code that will be shared with new board - Add the new board
2023-04-28clk: sunxi: Add NAND clocks and resetsSamuel Holland11-0/+43
Currently NAND clock setup is done in board code, both in SPL and in U-Boot proper. Add the NAND clocks/resets here so they can be used by the "full" NAND driver once it is converted to the driver model. The bit locations are copied from the Linux CCU drivers. Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-23Merge tag 'u-boot-rockchip-20230421' of ↵Tom Rini5-1/+139
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add rk3588 evb support; - Update pinctrl for rk3568 and rk3588; - Update rk3288 dts; - Update mmc support for rk3568 and rk3588; - Add rng support for rk3588; - Add DSI support for rk3568; - Some other misc fixes in dts, config, driver;
2023-04-21clk: rockchip: rk3588: Add limited TMCLK_EMMC clock supportJonas Karlman1-0/+2
The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock supportJonas Karlman1-0/+2
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock in assigned-clocks, add dummy support to set parent of this clock to the rk3568 cru driver. Fixes probe of pmic driver and missing regulators on affected boards, rk3568-evb and rk3568-rock-3a. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3588: Add support for sdmmc clocks in SPLJonas Karlman1-0/+125
Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: scmi: Add Kconfig option for SPLJonas Karlman2-1/+9
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options enabled and SPL_FIRMWARE disabled result in the following error. drivers/clk/clk_scmi.o: in function `scmi_clk_gate': drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate': drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate': drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_probe': drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel' make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make: *** [Makefile:2043: spl/u-boot-spl] Error 2 Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: rockchip: clk_rk3288: add PCLK_RKPWMJohan Jonker1-0/+1
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM instead of PCLK_PWM. They have the same pclk_cpu parent, so add PCLK_RKPWM to rk3288_clk_get_rate(). Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-20clk: starfive: Add StarFive JH7110 clock driverYanhong Wang7-0/+1004
Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-07clk: renesas: Add R8A779G0 V4H clock tablesHai Pham3-0/+319
Add clock tables for R8A779G0 V4H SoC from Linux next commit 058f4df42121 ("Add linux-next specific files for 20230228") There is an adjustment to the clock tables to make them easier suitable for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a plain PLL2. This should be sufficient until PLL2_VAR is implemented in the clock core. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver Treat PLL2 as non-PLL2_VAR for now]
2023-04-07clk: renesas: Add R8A779F0 S4 clock tablesHai Pham3-0/+257
Add clock tables for R8A779F0 S4 SoC Based on Linux commit 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support for R-Car S4-8") by Yoshihiro Shimoda and sync the tables up to Linux next commit 058f4df42121 ("Add linux-next specific files for 20230228") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver]
2023-04-07clk: renesas: Update R-Car Gen3 driver Gen4 supportMarek Vasut6-55/+138
Update R-Car Gen4 support in Gen3 clock driver. This patch renames the V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6 as well as SDSRC clock which use undocumented bits so far, and RPCSRC clock which uses its own more capable divider table. The Gen4 module standby and reset tables are also updated. This patch makes use of union to alias Gen3 and more extensive Gen4 PLL tables, as the driver cannot ever be instantiated on hardware that would identify itself as both Gen3 and Gen4. The V3U clock driver is updated to match Gen4 clock driver behavior, it is augmented with a more extensive PLL table and a valid MODEMR register offset. This supersedes "clk: renesas: Introduce R-Car Gen4 CPG driver" from Hai Pham as the R-Car Gen3 and Gen4 clock core drivers are extremely similar. That implementation was in turn based on Linux commit 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver") by Yoshihiro Shimoda . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-06clk: mpc83xx: Fix clocks for mpc832xChristophe Leroy1-0/+7
gd->arch.sdhc_clk only exists when CONFIG_FSL_ESDHC is set, so enclose it inside ifdefs. gd->arch.qe_clk and gd->arch.brg_clk must be populated when CONFIG_QE is set. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-03-30clk: imx8mp: add pwm clocks supportTommaso Merciai1-0/+24
Add clocks support for the PWM controllers. This is ported from Linux v6.3.0-rc1 Signed-off-by: Tommaso Merciai <tomm.merciai@gmail.com>
2023-03-30clk: imx8mp: Add EQoS MAC clockMarek Vasut1-0/+13
Add clock for the DWMAC EQoS block. This is used among other things to configure the MII clock via DM CLK. Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-28Merge tag 'u-boot-at91-2023.07-a' of ↵Tom Rini7-42/+303
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2023.07 cycle: This feature set includes the clock changes required for sam9x60 SoC to support USB host.
2023-03-27Merge branch 'master' into nextTom Rini3-6/+13
2023-03-27clk: at91: sam9x60: Add initial setup of UPLL and USBCK ratesSergiu Moga1-0/+30
In order for some of the functionalities, such as the USB clocks, to work properly we need some clocks to be properly initialised at the very beginning of booting. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: pmc: export clock setup to pmcClaudiu Beznea3-42/+64
Clock setup was intended for setting clocks at boot time on SAMA7G5, e.g. for root clocks like PLLs, that were used to feed IPs needed alive in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality to all at91 clocks as it may be necessary on other SoCs. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: sam9x60: Register the required clocks for USBSergiu Moga1-0/+33
Register into DM the clocks required to properly enable USB functionality within the bootloader. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-27clk: at91: Add support for sam9x60 USB clockSergiu Moga4-0/+176
Implement sam9x60 USB clock driver. This clock has three parents: PLLA, UPLL and MAINXTAL. The driver is aware of the three possible parents with the help of the two mux tables provied to the driver during the registration of the clock. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-03-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-shTom Rini1-4/+6
A single reset controller driver (part of the clock driver) fix for v2023.04 release.
2023-03-20clk: renesas: Pack reset identifier before look upMarek Vasut1-4/+6
The reset identifier must be processed via MOD_CLK_PACK() before it is used to look up register and bit within reset_regs or reset_clear_regs arrays, otherwise completely bogus register and bit is picked from the arrays, one which may even be out of range. Fixes: 326e05c5e21 ("clk: renesas: Add and enable CPG reset driver") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-19clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocksVasily Khoruzhick1-0/+3
Device tree contains assigned-clock-rates property for these, but default value will work just fine Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2023-03-19clk: rockchip: rk3588: Fix clk_aux16m in clock driverJonas Karlman1-2/+2
The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3568: Fix reset handlerPeter Geis1-0/+2
The reset handler for rk3568 is missing its private data. This leads to an abort when a reset is triggered. => reset resetting ... "Synchronous Abort" handler, esr 0x96000045 elr: 0000000000a2bc04 lr : 0000000000a2bbd4 (reloc) elr: 00000000eff9bc04 lr : 00000000eff9bbd4 x0 : 00000000fdd20000 x1 : 0000000014000001 x2 : 000000000000fdb9 x3 : 00000000edf77e88 x4 : 00000000edf50e78 x5 : 00000000edf77530 x6 : 000000000000001d x7 : 00000000edf8a1d0 x8 : 00000000ffffffd8 x9 : 0000000000000008 x10: 000000000000000d x11: 0000000000000006 x12: 000000000001869f x13: 0000000086c290c5 x14: 000000009118e878 x15: 0000000000000000 x16: 00000000eff9bbb8 x17: 0000000012f8c119 x18: 00000000edf50dc0 x19: 0000000000000000 x20: 0000000000000001 x21: 0000000000000000 x22: 00000000edf85900 x23: 0000000000000001 x24: 00000000effe8bbc x25: 0000000000000000 x26: 00000000edf85940 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000edf3c8e0 Code: d65f03c0 d5033fbf b9400661 529d9502 (b8216802) Resetting CPU ... Add the missing dev_set_priv to the rk3568 clk driver to fix this. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # radxa-cm3 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-03-18clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE cachingMarek Vasut2-10/+10
Do not cache the single CPG MODE register bit 12, instead cache the entire register value, and only pick the matching bit from the cached value when core clock of type MDSEL or PE are used. Both MDSEL and PE clock type currently define .offset field as 12 on Gen3, which means this code will use bit 12 on Gen3 again, however there are additional clock on Gen4 which use different bits, and having this flexibility in place now will be useful when adding Gen4. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-16Merge tag 'xilinx-for-v2023.07-rc1' of ↵Tom Rini1-2/+2
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.07-rc1 cmd: - Print results in hex instead of dec in smc command firmware: - Cover missing ZYNQMP_FIRMWARE dependencies fpga: - fix loads for unencrypted use case relocation - Add support for BE systems spi: - Fix xilinx_spi init reset sequence arasan nand: - Remove hardcoded bbt option - Set ofnode value xilinx: - Enable SMC command - Fix some sparse issues zynqmp: - Remove cdns,zynq-gem compatible string - Add optee node - Some DT cleanups zynq: - Some DT cleanups microblaze - Remove MANUAL_RELOC option
2023-03-14Merge tag 'v2023.04-rc4' into nextTom Rini5-3/+2265
Prepare v2023.04-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-10clk: renesas: Always select DM_RESET to prevent inobvious failure of ↵Marek Vasut1-0/+1
rst_gen3 subdriver The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3. The former depends on the clock framework, which is always enabled in this context of clock framework driver, while the later depends on reset framework which may not always be enabled. Ensure the reset framework is also always enabled to prevent inobvious early boot time bind failure of the CPG driver, which leads to system showing no activity and is difficult to debug. Note that one possible approach to debug this is to use CONFIG_DEBUG_UART and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-03-09arm64: zynqmp: Add missing ZYNQMP_FIRMWARE dependenciesAlgapally Santosh Sagar1-2/+2
There are missing Kconfig dependencies in the code which is using firmware interface. The commit 71efd45a5fc7 ("arm64: zynqmp: Change firmware dependency") add option to also disable ZYNQMP_FIRMWARE. But not all Kconfig dependencies were properly described and also sdhci and gem drivers didn't protect the code properly. So, add the missing ZYNQMP_FIRMWARE dependencies. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230201095553.11219-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-07clk: ast2600: Keep PLL power onDylan Hung1-2/+1
According to the PLL vendor, we should keep the PLL power on, so we shouldn't toggle the power-down bit during PLL initialization. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2023-02-28clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmcVasily Khoruzhick1-0/+3
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568 will return error in this case. Apparently, SDHCI silently ignores the error and as a result eMMC initialization fails. Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: pll: Add pll_rk3588 type for rk3588Jagan Teki1-3/+264
Add RK3588 pll set and get rate clock support. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: Add rk3588 clk supportJagan Teki2-0/+1997
Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-22clk: uniphier: Add missing USB SS-PHY clocksKunihiko Hayashi1-0/+5
The USB SS-PHY needs its own clock, however, some clocks don't have clock gates. Define missing clock entries for the PHY as reference clock. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-12clk: Allow clk_get_by_name() with NULL nameSamuel Holland1-5/+7
This allows devm_clock_get(dev, NULL) to work and get the first clock, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
2023-02-12clk: imx8mn: fix imx8mn_enet_phy_sels clocks listDario Binacchi1-1/+1
[backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b] According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK 001 - SYSTEM_PLL2_DIV20 010 - SYSTEM_PLL2_DIV8 011 - SYSTEM_PLL2_DIV5 100 - SYSTEM_PLL2_DIV2 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL_CLK 111 - AUDIO_PLL2_CLK ... ... ... while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for source select bits 101b. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-4-dario.binacchi@amarulasolutions.com
2023-02-12clk: imx: rename video_pll1 to video_pllDario Binacchi1-10/+10
[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6] Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
2023-02-12clk: imx8mn: rename vpu_pll to m7_alt_pllDario Binacchi1-1/+1
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df] The IMX8MN platform does not have any video processing unit (VPU), and indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there is no occurrence of its pll. From an analysis of the code and the RM itself, I think vpu pll is used instead of m7 alternate pll, probably for copy and paste of code taken from modules of similar architectures. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
2023-02-12clk: nuvoton: fix bug for calculate pll clockJim Liu1-1/+1
Fix bug for npcm7xx bmc calculate pll clock. PLLCON1 need to divide by 2. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Acked-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
2023-02-10Correct SPL uses of SANDBOX_CLK_CCFSimon Glass3-9/+9
This converts 12 usages of this option to the non-SPL form, since there is no SPL_SANDBOX_CLK_CCF defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL uses of CMD_CLKSimon Glass5-7/+7
This converts 7 usages of this option to the non-SPL form, since there is no SPL_CMD_CLK defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2023-02-02clk: renesas: rcar-gen3: Factor out CPG libraryHai Pham5-122/+230
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but similar enough to reuse code. Introduce a new CPG library, factor out the SD clock and RPC clock handling and hook them to the generic Gen3 CPG driver so we have an equal state. Based on Linux commit [1] and [2] by Wolfram Sang [1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library") [2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to the library") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Add rcar_clk_* prefix to all functions - Rebase on changes to clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function - Use u32_encode_bits/GENMASK bitfield ops
2023-02-02clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHIHai Pham3-5/+44
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on the other R-Car gen3 SoCs. Hence, new clock types are introduced respectively. Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead - Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types which is now part of common clock types in rcar-gen3-cpg.h instead
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-07 05:00:07 +0300