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path: root/drivers/clk
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2020-12-14dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass3-59/+59
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass18-44/+44
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass9-33/+33
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass10-19/+19
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass78-121/+121
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: Remove uses of device_bind_offset()Simon Glass2-13/+9
This function is not needed since the standard device_bind() can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind() to device_bind_offset()Simon Glass1-1/+1
This function is not necessary anymore, since device_bind_ofnode() does the same thing and works with both flattree and livetree. Rename it to indicate that it is special. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-11-17clk: sunxi: add compatible string for V3Icenowy Zheng1-0/+2
A new compatible string is introduced for V3 CCU, because it has a few extra features available. Add the compatible string to the clock driver. As the extra features are not touched, just share the description struct now. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-13rockchip: rk3399: Init clocks in U-Boot proper if SPL was not runAlper Nebi Yasak1-6/+16
It's possible to chainload U-Boot proper from the vendor firmware in rk3399 chromebooks, but the way the vendor firmware sets up clocks is somehow different than what U-Boot expects. This causes the display to stay devoid of content even though vidconsole claims to work (with patches in process of being upstreamed). This is meant to be a rk3399 version of commit d3cb46aa8c41 ("rockchip: Init clocks again when chain-loading") which can detect the discrepancy, but this patch instead checks whether SPL (and therefore the clock init) was run via the handoff functionality and runs the init if it was not. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-31Merge tag 'u-boot-rockchip-20201031' of ↵Tom Rini1-0/+20
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
2020-10-30clk: rockchip: rk3399: implement getting wdt/alive clocksJack Mitchell1-0/+20
In order to correctly calculate the designware watchdog timeouts, the watchdog clock is required. Implement required clocks to facilitate this. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-29dm: Use driver_info index instead of pointerSimon Glass1-2/+1
At present we use a 'node' pointer in the of-platadata phandle_n_arg structs. This is a pointer to the struct driver_info for a particular device, and we can use it to obtain the struct udevice pointer itself. Since we don't know the struct udevice pointer until it is allocated in memory, we have to fix up the phandle_n_arg.node at runtime. This is annoying since it requires that SPL's data is writable and adds a small amount of extra (generated) code in the dm_populate_phandle_data() function. Now that we can find a driver_info by its index, it is easier to put the index in the phandle_n_arg structures. Update dtoc to do this, add a new device_get_by_driver_info_idx() to look up a device by drive_info index and update the tests to match. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29dm: test: Add a test for of-platdata phandlesSimon Glass2-4/+4
We have a test in dtoc for this feature, but not one in U-Boot itself. Add a simple test that checks that the information comes through correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-26clk: kendryte: no need to check argument of free()Heinrich Schuchardt1-2/+1
free() checks if its argument is NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-10-22clk: ccf: replace the get_rate helperDario Binacchi1-25/+1
The 12d152620d commit fixed the get_rate helper because the set_parent one did not re-parent the clock device to the new parent. The 4d139f3838 commit allows you to remove this workaround by calling the clk_get_parent_rate routine. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-10-20clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar3-0/+315
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774E1 clock tablesBiju Das3-0/+365
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774B1 clock tablesBiju Das3-0/+343
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clockBiju Das1-0/+4
Add RPC entry into the R8A774A1 clock driver tables. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev1-2/+2
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev2-2/+2
clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: sam9x60: add support compatible with CCFClaudiu Beznea2-0/+650
Add SAM9X60 clock support compatible with CCF. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-16clk: at91: Include device_compat.h in compat.cTom Rini1-0/+1
Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16clk: sifive: Include device_compat.hSean Anderson1-7/+7
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-14treewide: Fix wrong CONFIG_IS_ENABLED() handlingAlper Nebi Yasak1-1/+1
CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix, e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being fixed every now and then, see: commit 71ba2cb0d678 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED") commit a5ada25e4213 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling") commit 5daf6e56d36c ("common: console: Fix duplicated CONFIG in silent env callback") commit 48bfc31b6484 ("MIPS: bootm: Fix broken boot_env_legacy codepath") Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running ':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-09clk: agilex: Additional membus writes for HPS PLLChee Hong Ang1-16/+78
Add additional membus writes to configure main and peripheral PLL for Agilex's clock manager. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09clk: agilex: Handle clock configuration differently in SPL and U-Boot properChee Hong Ang1-0/+10
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09clk: agilex: Add clock enable supportLey Foon Tan1-0/+6
Some drivers probing failed if clock enable function is not supported in clock driver. So, add clock enable function to clock driver to solve it. Return 0 (success) for *.enable function because all clocks are enabled by default in clock driver probe. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09clk: agilex: Add NAND clock supportLey Foon Tan1-0/+3
Add get nand_clk and nand_x clock support. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-06dm: add cells_count parameter in *_count_phandle_with_argsPatrick Delaunay1-2/+2
The cell_count argument is required when cells_name is NULL. This patch adds this parameter in live tree API - of_count_phandle_with_args - ofnode_count_phandle_with_args - dev_count_phandle_with_args This parameter solves issue when these API is used to count the number of element of a cell without cell name. This parameter allow to force the size cell. For example: count = dev_count_phandle_with_args(dev, "array", NULL, 3); Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-05Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini23-925/+4890
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
2020-09-30clk: add clock driver for SCMI agentsEtienne Carriere3-0/+108
This change introduces a clock driver for SCMI agent devices. When SCMI agent and SCMI clock drivers are enabled, SCMI agent binds a clock device for each SCMI clock protocol devices enabled in the FDT. SCMI clock driver is embedded upon CONFIG_CLK_SCMI=y. If enabled, CONFIG_SCMI_AGENT is also enabled. SCMI Clock protocol is defined in the SCMI specification [1]. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Lukasz Majewski <lukma@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-30riscv: clk: Add CLINT clock to kendryte clock driverSean Anderson1-0/+4
Another "virtual" clock (in the sense that it isn't configurable). This could possibly be done as a clock in the device tree, but I think this is a bit cleaner. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-09-24Merge tag 'xilinx-for-v2021.01' of ↵Tom Rini2-1/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.01 arm64: - Support for bigger U-Boot images compiled with PIE microblaze: - Extend support for LE/BE systems zynqmp: - Refactor silicon ID detection code with using firmware interface - Add support for saving variables based on bootmode zynqmp-r5: - Fix MPU mapping and defconfig setting. xilinx: - Minor driver changes: names alignment - Enable UBIFS - Minor DT and macros fixes - Fix boot with appended DT - Fix distro boot cmd: - pxe: Add fixing for platforms with manual relocation support clk: - fixed_rate: Add DM flag to support early boot on r5 fpga: - zynqmppl: Use only firmware interface and enable SPL build serial: - uartlite: Enable for ARM systems and support endians mmc: - zynq: Fix indentation net: - gem: Support for multiple phys - emac: Fix 64bit support and enable it for arm64 kconfig: - Setup default values for Xilinx platforms - Fix dependecies for Xilinx drivers - Source board Kconfig only when platform is enabled - Fix FPGA Kconfig entry with SPL - Change some defconfig values bindings: - Add binding doc for vsc8531
2020-09-23clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flagMichal Simek1-0/+1
fixed-rate driver is not different from clk_fixed_factor and it is required very early in boot that's why setup flag for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: drivers: Use '_' instead of '-' in driver nameMichal Simek1-1/+1
The most of drivers are using '_' instead of '-' in driver name. That's why sync up these names to be aligned. It looks quite bad to see both in use. It is visible via dm tree command. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22clk: at91: sama7g5: add clock supportClaudiu Beznea2-0/+1402
Add clock support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: pmc: add generic clock opsClaudiu Beznea2-0/+73
Add generic clock ops to be used by every AT91 PMC driver built on top of CCF. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-generic: add driver compatible with ccfClaudiu Beznea3-0/+209
Add clk-generic driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-peripheral: add driver compatible with ccfClaudiu Beznea3-0/+272
Add clk-peripheral compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-system: add driver compatible with ccfClaudiu Beznea3-1/+116
Add clk-system driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-programmable: add driver compatible with ccfClaudiu Beznea3-1/+226
Add clk-programmable driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-utmi: add support for sama7g5Claudiu Beznea2-1/+73
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via XTALF register. Values written at bits 2..0 in this register correspond to the on board crystal oscillator frequency. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-utmi: add driver compatible with ccfClaudiu Beznea3-0/+169
Add clk-utmi driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-master: add support for sama7g5Claudiu Beznea2-1/+182
Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has multiple master clocks feeding different subsystems. One of them feeds image subsystem and is changeable based on image subsystem needs. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-master: add driver compatible with ccfClaudiu Beznea3-1/+178
Add clk-master driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: sam9x60-pll: add driver compatible with ccfClaudiu Beznea4-0/+486
Add sam9x60-pll driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: clk-main: add driver compatible with ccfClaudiu Beznea3-1/+398
Add clk-main driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: sckc: add driver compatible with ccfClaudiu Beznea2-1/+173
Add sckc driver compatible with common clock framework. Driver implements slow clock support for SAM9X60 compatible IPs (in this list it is also present SAMA7G5's slow clock IP). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22clk: at91: move clock code to compat.cClaudiu Beznea16-1163/+1030
Move clock code to compat.c to allow switching to CCF without mixing CCF code with non CCF code. This prepares the field for next commits. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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