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2019-12-09Merge tag 'u-boot-imx-20191209' of ↵Tom Rini1-1/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - imx8qxp_mek: increase buffer sizes and args number - Fixes for imx7ulp - imx8mm: Fix the first root clock in imx8mm_ahb_sels[] - colibri_imx7: reserve DDR memory for Cortex-M4 - vining2000: fixes and convert to ethernet DM - imx8m: fix rom version check to unbreak some B0 chips - tbs2910: Disable VxWorks image booting support
2019-12-06clk: imx: imx8mm: Fix the first root clock in imx8mm_ahb_sels[]Frieder Schrempf1-1/+1
The 24MHz oscillator clock is referenced by "clock-osc-24m" and not "osc_24m". Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-12-03clk: mediatek: add driver for MT8518mingming lee2-0/+1559
Add clock driver for MediaTek MT8518 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03common: Move get_ticks() function out of common.hSimon Glass1-0/+1
This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03Move strtomhz() to vsprintf.hSimon Glass2-0/+2
At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-17rockchip: clk: Add clk driver for rk3308Finley Xiao2-0/+1073
Add clk controller driver for RK3308 SOC. This patch depends on Elaine's pll patch[0]. [0]http://patchwork.ozlabs.org/patch/1183718/ Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: pll: add common pll setting funcsElaine Zhang2-0/+361
Common PLL setup function, compatible with different SOC. Mainly for the subsequent new SOC use. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: fix wrong CONFIG_IS_ENABLED handlingHeiko Stuebner8-8/+8
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so without the leading CONFIG_. The clock drivers all wrongly check for CONFIG_RESET_ROCKCHIP, fix that Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: rv1108: remove duplicate reset initHeiko Stuebner1-14/+2
rockchip_reset_bind() already does the needed init for the reset registers, only referenced the wrong cru structure. So we can get rid of the open-coded reset init and just fix the correct cru reference. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: add px30 clock driverKever Yang2-0/+1631
The px30 contains 2 separate clock controllers, pmucru and cru. Add drivers for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-12Merge tag 'u-boot-imx-20191105' of ↵Tom Rini4-0/+479
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191105 ------------------- i.MX8MN SoC support ROM API image download support i.MX8MM enet enabling
2019-11-11Merge tag 'u-boot-rockchip-20191110' of ↵Tom Rini1-0/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Add support for rockchip pmic rk805,rk809, rk816, rk817 - Add rk3399 board Leez support - Fix bug in rk3328 ram driver - Adapt SPL to support ATF bl31 with entry at 0x40000 - Fix the u8 type comparision with '-1'. - Fix checkpatch warning for multi blank line and review signature.
2019-11-10clk: rockchip: rk3328: Configure CPU clockSimon South1-0/+2
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-08clk: clk-ti-sci: Notify AVS driver upon setting clock rateKeerthy1-0/+5
Notify AVS driver upon setting clock rate so that voltage is changed accordingly. Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-05clk: imx: imx8mm: add set_parent callbackPeng Fan1-0/+19
Add set_parent callback, then assigned-clock-parents in dts could be work. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05clk: imx8mm: add enet clkPeng Fan1-0/+27
Add enet ref/timer/PHY_REF/root clk which are required to make enet function well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05clk: imx: add i.MX8MN ccf driverPeng Fan3-0/+433
Add i.MX8MM ccf driver support. Modifed from Linux Kernel 5.3.0-rc1, drop some entries that not used in U-Boot and adapt to U-Boot CCF style. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Lukasz Majewski <lukma@denx.de>
2019-10-30Merge tag 'u-boot-clk-23Oct2019' of ↵Tom Rini5-23/+279
https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Add I2C clocks for i.MX6Q CCF driver - Fix check in clk_set_default_parents() - Managed API to get clock from device tree - Fixes for core clock code (including sandbox regression tests)
2019-10-26Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsTom Rini3-0/+162
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
2019-10-25clk: add clock driver for MediaTek MT76x8 platformWeijie Gao3-0/+162
This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-24arm64: zynqmp: Switch to xlnx-zynqmp-clk headerMichal Simek1-1/+0
Use prepared header instead of hardcoded values. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: versal: Rename versal_pm_request to xilinx_pm_requestMichal Simek1-7/+7
Use generic name instead of Versal specific because this should be also used on ZynqMP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: versal: Clean pm_api_id usageMichal Simek1-0/+1
Copy enum values from platform code to firmware code. IDs are shared between ZynqMP and Versal. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-22test: clk: test clock self assignmentJean-Jacques Hiblot1-0/+22
Make sure that the clock self-assignment works by having a clock of clk-sbox be configured automatically when clk-sbox is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22drivers: clk: Fix using assigned-clocks in the node of the clock it sets upJean-Jacques Hiblot1-6/+42
This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22test: clk: Update tests to also check the managed APIJean-Jacques Hiblot2-9/+91
Add a few more clocks the clk_sandbox clock provider and get them using the managed API. Make sure they are released when the device is removed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22drivers: clk: Add a managed API to get clocks from the device-treeJean-Jacques Hiblot1-0/+48
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the device-tree. The clocks is automatically released and the data structure freed when the device is unbound. Also add devm_clk_put() to release the clock and free the data structure manually. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22drivers: clk: Handle gracefully NULL pointersJean-Jacques Hiblot1-7/+36
Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22clk: Add support for I2C clocks on NXP's imx6q SoC which use CCFLukasz Majewski2-0/+39
This change adds support for I2C clock modeled in CCF. This code intention is to only enable those clocks in the I2C driver with default settings. For that reason the "busy" versions of clocks reuse the generic approach and would need to be updated when one wants to adjust the I2C clock frequency in U-Boot. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-22clk: Fix error check in clk_set_default_parents()Jean-Jacques Hiblot1-1/+1
According to the documentation in clk.h, clk_set_parent() return the new rate of the clock or a negative error code. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-18clk: meson-sm1: add compatibleNeil Armstrong1-0/+1
The SM1 clock controller is almost identical to the G12A and so far the differences don't matter. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18clk: meson: g12a: add support for VPU/HDMI clocksNeil Armstrong1-17/+603
Add necessary clock support to set up clock for the VPU and HDMI support. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-11clk: cdce9xx: add support for cdce9xx clock synthesizerTero Kristo3-0/+262
Add support for CDCE913/925/937/949 family of devices. These are modular PLL-based low cost, high performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. The initial version of the driver does not support programming of the PLLs, and thus they run in the bypass mode only. The code is loosely based on the linux kernel cdce9xx driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-09Merge tag 'xilinx-for-v2020.01' of ↵Tom Rini3-0/+756
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file
2019-10-08clk: versal: Add clock driver supportSiva Durga Prasad Paladugu3-0/+755
This patch adds clock driver support for Versal platform. The clock driver queries and performs clock operations using PLM firmware by communicating with it using SMC calls. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08zynqmp: firmware: Add Xilinx ZynqMP firmware driverRajan Vaja1-0/+1
Add simple ZynqMP firmware drive to populate child nodes under zynqmp_firmware DT node. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08ARM: at91: Rename sama5_sfr.h to at91_sfr.hTudor Ambarus1-1/+1
The Special Function Registers (SFR) are present in sam9x5 and sam9x60 too, rename sama5_sfr to at91_sfr.h. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-09-11rockchip: clk: rk3399: remove clk_enable()Kever Yang1-37/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3368: remove clk_enable()Kever Yang1-19/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3328: remove clk_enable()Kever Yang1-12/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3288: remove clk_enable()Kever Yang1-23/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-05clk: aspeed: Add support for SD clockEddie James1-0/+27
Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-08-29Merge tag 'u-boot-amlogic-20190828' of ↵Tom Rini1-0/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - add missing g12b clock driver compatible, fixing odroid-n2 usb support
2019-08-28clk: meson-g12b: add compatibleMark Kettenis1-0/+1
The G12B clock controller is almost identical to the G12A and so far the differences don't matter. Adding the G12B compatible makes USB work on the Odroid-N2. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-27stm32mp1: clk: use gd to store frequency informationPatrick Delaunay1-7/+9
Use existing gd structure to store frequency information which can be used in drivers or arch without new request. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: clk: remove debug tracesPatrick Delaunay1-17/+4
Remove many debug trace. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-26Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford1-0/+1
Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-24Merge tag 'u-boot-rockchip-20190823' of ↵Tom Rini1-0/+12
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - remove rk3288 fennec board - remove SPL raw image support for Rockchip SoCs - add common misc_init_r() for ethaddr from cpuid - enable USB HOST support for rk3328 - unify code for finding a valid gpt in part driver
2019-08-23rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang1-0/+12
Required to successfully probe the ehci generic driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-22clk: imx: add i.MX8MM clk driverPeng Fan2-0/+417
Add i.MX8MM clk driver support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
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