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2023-01-18event: Correct dependencies on the EVENT frameworkTom Rini1-1/+0
The event framework is just that, a framework. Enabling it by itself does nothing, so we shouldn't ask the user about it. Reword (and correct typos) around this the option and help text. This also applies to DM_EVENT and EVENT_DYNAMIC. Only EVENT_DEBUG and CMD_EVENT should be visible to the user to select, when EVENT is selected. With this, it's time to address the larger problems. When functionality uses events, typically via EVENT_SPY, the appropriate framework then must be select'd and NOT imply'd. As the functionality will cease to work (and so, platforms will fail to boot) this is non-optional and where select is appropriate. Audit the current users of EVENT_SPY to have a more fine-grained approach to select'ing the framework where used. Also ensure the current users of event_register and also select EVENT_DYNAMIC. Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Reported-by: Oliver Graute <Oliver.Graute@kococonnector.com> Reported-by: Francesco Dolcini <francesco.dolcini@toradex.com> Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Fixes: 42fdcebf859f ("event: Convert misc_init_f() to use events") Fixes: c5ef2025579e ("dm: fix DM_EVENT dependencies") Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-18dm: treewide: Do not opencode uclass_probe_all()Michal Suchanek1-16/+4
We already have a function for probing all devices of a specific class, use it. Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-29dm: core: Drop ofnode_is_available()Simon Glass2-2/+2
This function is also available as ofnode_is_enabled(), so use that instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-23cpu: add basic cpu driver for MediaTek ARM chipsWeijie Gao2-0/+87
Add basic CPU driver used to retrieve CPU model information. Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-13cpu: microblaze: add error handling in microblaze_cpu_get_desc()Ovidiu Panait1-1/+3
Check snprintf() return value for errors. Make microblaze_cpu_get_desc() directly return snprintf() error code if ret < 0. Otherwise, if the return value is greater than or equal to size, the resulting string is truncated, so return -ENOSPC. Fixes: 816226d27e ("cpu: add CPU driver for microblaze") Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-08-10common: Drop display_options.h from common headerSimon Glass1-0/+1
Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-06-24cpu: add CPU driver for microblazeOvidiu Panait3-0/+190
Add a basic CPU driver that retrieves information about the microblaze CPU core. cpu_ops handlers are implemented so that the "cpu" command can work properly: U-Boot-mONStR> cpu list 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 U-Boot-mONStR> cpu detail 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 ID = 0, freq = 50 MHz: L1 cache, MMU Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from linux. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24cpu-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOCOvidiu Panait1-0/+30
Relocate cpu_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-04-26cpu: 83xx: Add missing dependency on CPU_MPC83XXMichal Simek1-1/+1
It looks quite weird that for non PPC platforms cpu driver for MPC83xx can be selected. That's why define proper dependency. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-09-25sandbox: correct cpu nodesHeinrich Schuchardt1-1/+1
The cpu nodes in arch/sandbox/dts/test.dts should conform to the devicetree specification: * property device_type must be set to "cpu" * the reg property must be provided * the cpu nodes must have an address Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-21cpu: at91: add compatible for ARM9260EJ-SClaudiu Beznea1-0/+1
The crystal, CPU and master clock were not displayed correctly on SAM9X60 after adding CCF clock support. Add compatible for ARM926EJ-S to fix this. Reported-by: Eugen Hristev <eugen.hristev@microchip.com> Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass2-0/+2
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-12-14dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass6-19/+19
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2-9/+9
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass6-6/+6
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass5-5/+5
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-05Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini2-0/+124
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
2020-10-05cpu: at91: add driver for CPUClaudiu Beznea2-0/+124
Add basic CPU driver use to retrieve information about CPU itself. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-30timer: Add a test for timer_timebase_fallbackSean Anderson1-7/+32
To test this function, sandbox CPU must set cpu_platdata.timebase_freq on bind. It also needs to expose a method to set the current cpu. I also make some most members of cpu_sandbox_ops static. On the timer side, the device tree property sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-25cpu: Convert the methods to use a const udevice *Simon Glass6-32/+34
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini6-34/+32
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-20cpu: Convert the methods to use a const udevice *Simon Glass6-32/+34
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-01riscv: cpu: check and append L1 cache to cpu featuresSagar Shrikant Kadam1-0/+12
All cpu cores within FU540-C000 having split I/D caches. Set the L1 cache feature bit using the i-cache-size or d-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core. => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-01riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bitSagar Shrikant Kadam1-4/+1
The conditional check to read "mmu-type" from the device tree is not rightly handled due to which the cpu feature doesn't include CPU_FEAT_MMU even if it's corresponding entry is present in the device tree. The initialization of cpu features is now taken care in cpu-uclass driver, so no need to zero out cpu_freq in riscv_cpu driver and can be removed. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-01uclass: cpu: fix to display proper CPU featuresSagar Shrikant Kadam1-0/+3
The cmd "cpu detail" fetches uninitialized cpu feature information and thus displays wrong / inconsitent details as below. For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it. => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 The L1 cache or MMU entry seen above is also displayed inconsistently. So initialize cpu information to zero into cpu-uclass itself so that similar issues can be avoided for other CPU drivers. We now see correct features as: => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-01riscv: Enable cpu clock if it is presentSean Anderson1-0/+20
The cpu clock is probably already enabled if we are executing code (though we could be executing from a different core). This patch prevents the cpu clock or its parents from being disabled. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01riscv: Try to get cpu frequency from a "clocks" node if it existsSean Anderson1-1/+18
Instead of always using the "clock-frequency" property to determine cpu frequency, try using a clock in "clocks" if it exists. This patch also fixes a bug where there could be spurious higher frequencies if sizeof(u32) != sizeof(ulong). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-22cpu: imx8: use intended cpu-thermal device when getting temp valueAnatolij Gustschin1-25/+25
This fixes getting DT alert and critical pdata values in imx_scu_thermal driver. On i.MX8QXP using not initialized alert pdata value resulted in boot hang and endless loop outputting: CPU Temperature (47200C) has beyond alert (0C), close to critical (0C) waiting... While at it, preset CPU type values once to avoid multiple calls of device_is_compatible() for same property. Fixes: 3ee6ea443eb4 ("cpu: imx_cpu: Print the CPU temperature for iMX8QM A72") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-22cpu: imx8: fix type and rate detectionAnatolij Gustschin1-6/+6
CPU type and rate detection is broken, for A35 cpu we get A53: ... sc_pm_get_clock_rate: resource:0 clk:2: res:3 Could not read CPU frequency: -22 CPU: NXP i.MX8QXP RevB A53 at 0 MHz at 47C Fixes: 55bc96f3b675 ("cpu: imx8: fix get core name and rate") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass4-0/+4
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass3-0/+3
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop init.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop net.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-03cpu: imx8: show RevC instead of Rev? at boot logFrank Li1-0/+2
Add REVC informaiton. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03cpu: imx_cpu: Print the CPU temperature for iMX8QM A72Ye Li1-6/+12
iMX8QM registers two thermal devices for CPUs, get the temperature from "cpu-thermal1" device for A72 Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03cpu: imx8: fix get core name and ratePeng Fan1-10/+17
When current cpu is A53, using is_cortex_a53 could not detect A72 information, so check cpu device compatible property to get the correct information. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03cpu: imx8: support a72 as boot cpuPeng Fan1-0/+19
Support booting i.MX8QM with A72 as boot cpu Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03cpu: imx8: reimplement get cpu countPeng Fan1-1/+18
Return 4 is not correct on i.MX8DX/DXL/8QM and etc. we need to count available cpu node with device_type "cpu". Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03cpu: sandbox: support is_currentPeng Fan1-0/+9
Support querying whether U-Boot is running on current cpu Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03uclass: cpu: Add new API to get udevice for current CPUPeng Fan1-0/+34
When running on SoC with multiple clusters, the boot CPU may not be fixed, saying booting from cluster A or cluster B. Add a API that can return the udevice for current boot CPU. Cpu driver needs to implement is_current_cpu interface for this feature, otherwise the API only returns the first udevice in cpu uclass. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2020-04-16cpu: Support querying the address widthSimon Glass1-0/+1
Different CPUs may support different address widths, meaning the amount of memory they can address. Add a property for this to the cpu_info struct. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-03Move strtomhz() to vsprintf.hSimon Glass1-0/+1
At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-10-08imx8: move i.MX8 cpu desc code to drivers/cpu/imx8_cpu.cPeng Fan2-0/+183
Move cpu desc code to cpu driver directory and name it imx8_cpu.c No functional change. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-09-03riscv: cpu: Skip unavailable hart in the get_count() opBin Meng1-0/+4
We should not count in hart that is marked as not available in the device tree in riscv_cpu_get_count(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27cpu: Bind timer driver for boot hartAtish Patra1-3/+4
Currently, timer driver is bound only for hart0. There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18cpu: Add a RISC-V CPU driverBin Meng3-0/+123
This adds a driver for RISC-V CPU. Note the driver will bind a RISC-V timer driver if "timebase-frequency" property is present in the device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-11-14cpu: mpc83xx: Remove unnecessary characters in the description stringBin Meng1-1/+1
The description string should not contain unnecessary characters, like the ending '\n' or the leading 'CPU:'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay1-2/+2
Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-09-18cpu: Add MPC83xx CPU driverMario Six4-0/+483
Add a CPU driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
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