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Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
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Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
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JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
ddr
/
altera
/
sequencer.c
Age
Commit message (
Expand
)
Author
Files
Lines
2021-02-25
dm: ddr: socfpga: don't assign values that are not used
Heinrich Schuchardt
1
-7
/
+0
2020-05-19
common: Drop log.h from common header
Simon Glass
1
-0
/
+1
2020-02-05
ddr: altera: Add DDR2 support to Gen5 driver
Marek Vasut
1
-36
/
+158
2019-07-21
dm: ddr: socfpga: fix gen5 ddr driver to not use bss
Simon Goldschmidt
1
-635
/
+711
2019-04-17
arm: socfpga: move gen5 SDR driver to DM
Simon Goldschmidt
1
-1
/
+8
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2018-01-25
ddr: altera: silence PHY calibration unless in debug mode
Goldschmidt Simon
1
-4
/
+4
2016-04-20
ddr: altera: Repair DQ window centering code
Marek Vasut
1
-8
/
+7
2016-04-20
ddr: altera: Staticize global variables
Marek Vasut
1
-4
/
+4
2016-04-20
ddr: altera: Make DLEVEL behavior inclusive
Marek Vasut
1
-66
/
+66
2016-04-20
ddr: altera: Zero DM IN delay in scc_mgr_zero_group()
Marek Vasut
1
-3
/
+13
2016-04-20
ddr: altera: Remove unnecessary ODT mode config
Marek Vasut
1
-1
/
+0
2016-04-20
ddr: altera: Remove unnecessary update of the SCC
Marek Vasut
1
-1
/
+0
2016-04-20
ddr: altera: Fix scc_mgr_set() argument order
Marek Vasut
1
-1
/
+1
2016-04-20
ddr: altera: Tweak DQS tracking enable handling
Marek Vasut
1
-2
/
+5
2016-04-20
ddr: altera: Replace ad-hoc constant with macro
Marek Vasut
1
-2
/
+2
2015-08-23
ddr: altera: Repair uninited variable
Marek Vasut
1
-1
/
+1
2015-08-23
ddr: altera: Replace float multiplication with integer one
Marek Vasut
1
-1
/
+1
2015-08-08
ddr: altera: sequencer: Clean checkpatch issues
Marek Vasut
1
-71
/
+88
2015-08-08
ddr: altera: sequencer: Clean data types
Marek Vasut
1
-48
/
+48
2015-08-08
ddr: altera: sequencer: Pluck out misc macros from code
Marek Vasut
1
-22
/
+15
2015-08-08
ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL
Marek Vasut
1
-4
/
+4
2015-08-08
ddr: altera: sequencer: Zap VFIFO_SIZE
Marek Vasut
1
-4
/
+4
2015-08-08
ddr: altera: sequencer: Wrap misc remaining macros
Marek Vasut
1
-0
/
+2
2015-08-08
ddr: altera: sequencer: Pluck out IO_* macros from code
Marek Vasut
1
-101
/
+100
2015-08-08
ddr: altera: sequencer: Wrap IO_* macros
Marek Vasut
1
-0
/
+2
2015-08-08
ddr: altera: sequencer: Pluck out RW_MGR_* macros from code
Marek Vasut
1
-146
/
+146
2015-08-08
ddr: altera: sequencer: Wrap RW_MGR_* macros
Marek Vasut
1
-0
/
+4
2015-08-08
ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init
Marek Vasut
1
-6
/
+8
2015-08-08
ddr: altera: sequencer: Zap unused params and macros
Marek Vasut
1
-48
/
+1
2015-08-08
ddr: altera: sequencer: Move qts-generated files to board dir
Marek Vasut
1
-4
/
+9
2015-08-08
ddr: altera: Clean up of delay_for_n_mem_clocks() part 5
Marek Vasut
1
-3
/
+5
2015-08-08
ddr: altera: Clean up of delay_for_n_mem_clocks() part 4
Marek Vasut
1
-12
/
+5
2015-08-08
ddr: altera: Clean up of delay_for_n_mem_clocks() part 3
Marek Vasut
1
-18
/
+6
2015-08-08
ddr: altera: Clean up of delay_for_n_mem_clocks() part 2
Marek Vasut
1
-8
/
+10
2015-08-08
ddr: altera: Clean up of delay_for_n_mem_clocks() part 1
Marek Vasut
1
-14
/
+13
2015-08-08
ddr: altera: Minor clean up of rw_mgr_mem_handoff()
Marek Vasut
1
-7
/
+8
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo()
Marek Vasut
1
-22
/
+27
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()
Marek Vasut
1
-38
/
+21
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()
Marek Vasut
1
-13
/
+18
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3
Marek Vasut
1
-1
/
+11
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2
Marek Vasut
1
-39
/
+36
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1
Marek Vasut
1
-205
/
+201
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5
Marek Vasut
1
-1
/
+6
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4
Marek Vasut
1
-6
/
+7
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
Marek Vasut
1
-3
/
+2
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2
Marek Vasut
1
-79
/
+88
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
Marek Vasut
1
-61
/
+63
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11
Marek Vasut
1
-1
/
+10
2015-08-08
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10
Marek Vasut
1
-4
/
+7
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