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2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk1-1/+0
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-22ddr: altera: use KBUILD_BASENAME instead of __FILE__Marek Vasut1-4/+4
The KBUILD_BASENAME contains just the name of the compiled module, in this case 'sequencer', rather than a full path to the compiled file. Use it to prevent pulling the full path into the U-Boot binary, which is useless and annoying. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee4-1/+2371
The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25ddr: socfpga: Enable memory test on memory size less than 1GBTien Fong Chee1-3/+21
Minimum 1GB memory size is required in current memory test, so this patch improves the memory test for processing memory size less than 1GB, and the size in power of two. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-03-08arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim1-3/+3
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-02-25dm: ddr: socfpga: don't assign values that are not usedHeinrich Schuchardt1-7/+0
The values of left_edge[0] and right_edge[0] are overwritten before they are used. Remove the superfluous assignments. Fixes: 285b3cb939a8 ("dm: ddr: socfpga: fix gen5 ddr driver to not use bss") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass4-0/+4
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05dm: Use access methods for dev/uclass private dataSimon Glass4-5/+5
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2020-12-14dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass5-23/+23
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2-4/+4
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass4-7/+7
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2-4/+4
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-17treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada4-6/+6
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass2-0/+2
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop linux/delay.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass6-0/+6
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop init.h from common headerSimon Glass2-0/+2
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop net.h from common headerSimon Glass2-0/+2
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-11Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini2-0/+2
sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions
2020-02-06dm: core: Create a new header file for 'compat' featuresSimon Glass2-0/+2
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05ddr: altera: Add DDR2 support to Gen5 driverMarek Vasut3-38/+163
Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated by Quartus are named differently than the DDR3 ones, use anon unions to store them in the same structures, without growing their size. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-18common: Move hang() to the same header as panic()Simon Glass3-0/+3
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17common: Move RAM-sizing functions to init.hSimon Glass2-0/+2
These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC AccessThor Thayer2-6/+6
The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled. The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07arm: socfpga: stratix10: Enable SMMU accessThor Thayer1-0/+14
Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07ddr: altera: agilex: Add SDRAM driver for AgilexLey Foon Tan5-3/+174
Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07ddr: altera: Restructure Stratix 10 SDRAM driverLey Foon Tan5-443/+493
Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan1-1/+1
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move firewall code to firewall fileLey Foon Tan1-1/+1
Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan2-10/+8
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-12-03common: Move some cache and MMU functions out of common.hSimon Glass2-0/+2
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-21ddr: socfpga: gen5: constify altera_gen5_sdram_opsSimon Goldschmidt1-1/+1
Make the function pointer struct const, as it does not need to be writable. This doesn't really change anything other than moving this variable to a different section. No functional change. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-07-21dm: ddr: socfpga: fix gen5 ddr driver to not use bssSimon Goldschmidt2-642/+740
This driver uses bss from SPL board_init_f(). Change it to move all the data from bss to a common struct allocated on the stack (64 byte). In addition to saving 28 bytes of bss, the code even gets 264 bytes smaller. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-06arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan3-77/+360
Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-06ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan2-3/+4
Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17ddr: altera: Stratix10: Add ECC memory scrubbingLey Foon Tan1-0/+81
Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17ddr: altera: Stratix10: Add multi-banks DRAM size checkLey Foon Tan1-5/+41
Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17ddr: altera: stratix10: Move SDRAM size check to SDRAM driverLey Foon Tan1-0/+15
Move SDRAM size check to SDRAM driver. sdram_calculate_size() is called in SDRAM initialization already, avoid calling twice in size check function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17arm: socfpga: move gen5 SDR driver to DMSimon Goldschmidt4-16/+173
To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-03-10ddr: socfpga: Clean up ddr_setup()Marek Vasut1-28/+15
Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-10ddr: socfpga: Clean up EMIF resetMarek Vasut1-26/+7
The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-10ddr: socfpga: Fix EMIF clear timeoutMarek Vasut1-14/+11
The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09ddr: socfpga: Fix newline in debug print on A10Marek Vasut1-1/+1
The debug print is missing a newline, add it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09ddr: socfpga: Fix IO in Arria10 DDR driverMarek Vasut1-3/+3
The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2018-09-15socfpga: stratix10: fix sdram_calculate_sizeDalon Westergreen1-2/+2
Incorrect type of size variable results in 0 being returned for sdram sizes greater than or equal to 4GB. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2018-07-12ddr: altera: Add ECC DRAM scrubbing support for Arria10Marek Vasut1-0/+27
The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10Marek Vasut1-25/+0
This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only difference is the part which configures OCRAM as cachable, which doesn't really work as it covers more than the OCRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan2-0/+389
Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-20SPDX: Fixup SPDX tags in a few new filesTom Rini1-2/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-18configs: Add DDR Kconfig support for Arria 10Tien Fong Chee1-1/+1
This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
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