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path: root/drivers/ddr
AgeCommit message (Expand)AuthorFilesLines
2016-04-20ddr: altera: Remove unnecessary ODT mode configMarek Vasut1-1/+0
2016-04-20ddr: altera: Remove unnecessary update of the SCCMarek Vasut1-1/+0
2016-04-20ddr: altera: Fix DRAM end value in protection ruleMarek Vasut1-1/+1
2016-04-20ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut1-1/+1
2016-04-20ddr: altera: Tweak DQS tracking enable handlingMarek Vasut1-2/+5
2016-04-20ddr: altera: Replace ad-hoc constant with macroMarek Vasut1-2/+2
2016-03-27Fix typo choosen in comments and printf logsAlexander Merkle1-2/+2
2016-03-24arm: mvebu: Fix ddr3_init() cpu configDirk Eibach1-2/+0
2016-03-21driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu1-5/+39
2016-03-21driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu2-7/+63
2016-02-06Use correct spelling of "U-Boot"Bin Meng1-1/+1
2016-02-02drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal4-0/+497
2016-01-25drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout1-0/+1
2016-01-25driver/ddr/fsl: Add workaround for A009663Shengzhou Liu1-0/+10
2016-01-25fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu1-0/+18
2016-01-19Add more SPDX-License-Identifier tagsTom Rini10-30/+10
2016-01-16ddr: altera: Init the rule ID in debug codeMarek Vasut1-0/+1
2016-01-14mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter2-11/+11
2016-01-14axp: Fix debugging support in DDR3 write levelingPhil Sutter1-2/+2
2016-01-14arm: mvebu: Make ECC support configurable on Armada XPStefan Roese2-0/+8
2016-01-14arm: mvebu: ddr: Fix compilation warningStefan Roese2-17/+0
2015-12-15move erratum a008336 and a008514 to soc specific fileYao Yuan1-34/+0
2015-12-14fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu1-3/+6
2015-12-14driver/ddr/fsl: Update timing config for heavy loadYork Sun1-2/+24
2015-12-14driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun1-7/+15
2015-12-14driver/ddr/fsl: Update MR5 RTT parkYork Sun1-4/+15
2015-12-14driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun1-0/+3
2015-12-14driver/ddr/fsl: Update DDR4 RTT valuesYork Sun1-2/+235
2015-11-30drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun1-12/+12
2015-11-30drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2-0/+41
2015-11-30armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha1-2/+2
2015-11-30armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha1-2/+2
2015-11-18arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach1-5/+2
2015-11-18arm: mvebu: a38x: Remove unsupported topologiesKevin Smith2-77/+0
2015-11-10Various Makefiles: Add SPDX-License-Identifier tagsTom Rini1-3/+1
2015-10-30drivers/ddr/fsl_ddr: Make SR_IE configurableJoakim Tjernlund1-1/+1
2015-09-12bitops: introduce BIT() definitionHeiko Schocher1-2/+0
2015-08-23ddr: altera: Repair uninited variableMarek Vasut1-1/+1
2015-08-23ddr: altera: Replace float multiplication with integer oneMarek Vasut1-1/+1
2015-08-17arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2-2/+2
2015-08-17arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese1-1/+1
2015-08-08ddr: altera: sequencer: Clean checkpatch issuesMarek Vasut1-71/+88
2015-08-08ddr: altera: sequencer: Clean data typesMarek Vasut1-48/+48
2015-08-08ddr: altera: sequencer: Pluck out misc macros from codeMarek Vasut1-22/+15
2015-08-08ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VALMarek Vasut2-49/+4
2015-08-08ddr: altera: sequencer: Zap VFIFO_SIZEMarek Vasut2-7/+4
2015-08-08ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut1-0/+2
2015-08-08ddr: altera: sequencer: Pluck out IO_* macros from codeMarek Vasut1-101/+100
2015-08-08ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut1-0/+2
2015-08-08ddr: altera: sequencer: Pluck out RW_MGR_* macros from codeMarek Vasut2-154/+154
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