index
:
starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
fpga
/
Makefile
Age
Commit message (
Expand
)
Author
Files
Lines
2020-10-09
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
Chee Hong Ang
1
-1
/
+1
2019-10-08
arm64: versal: fpga: Add PL bit stream load support
Siva Durga Prasad Paladugu
1
-0
/
+1
2018-12-20
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
Ang, Chee Hong
1
-0
/
+1
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-3
/
+1
2017-07-26
arm: socfpga: Add FPGA driver support for Arria 10
Tien Fong Chee
1
-0
/
+1
2017-07-26
arm: socfpga: Restructure FPGA driver in the preparation to support A10
Tien Fong Chee
1
-0
/
+1
2016-09-22
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP
Siva Durga Prasad Paladugu
1
-0
/
+1
2016-03-24
fpga: altera: Add StratixV support
Stefan Roese
1
-0
/
+1
2014-10-06
arm: socfpga: fpga: Add SoCFPGA FPGA programming interface
Pavel Machek
1
-0
/
+1
2013-11-17
drivers: descend into sub directories only when it is necessary
Masahiro Yamada
1
-2
/
+0
2013-10-31
drivers: convert makefiles to Kbuild style
Masahiro Yamada
1
-33
/
+11
2013-07-24
Add GPL-2.0+ SPDX-License-Identifier to source files
Wolfgang Denk
1
-17
/
+1
2013-05-06
fpga: zynq: Add support for loading bitstream
Michal Simek
1
-0
/
+1
2010-11-17
Switch from archive libraries to partial linking
Sebastien Carlier
1
-2
/
+2
2010-10-13
FPGA: add support for downloading Lattice bitstream
Stefano Babic
1
-0
/
+1
2008-12-06
FPGA: move fpga drivers to drivers/fpga
Jean-Christophe PLAGNIOL-VILLARD
1
-0
/
+58