starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-10-10	fpga: virtex2: Use logging feature instead of FPGA_DEBUG	Alexander Dahl	1	-39/+30
2022-10-10	fpga: spartan3: Use logging feature instead of FPGA_DEBUG	Alexander Dahl	1	-43/+37
2022-10-10	fpga: spartan2: Use logging feature instead of FPGA_DEBUG	Alexander Dahl	1	-43/+37
2022-10-10	fpga: ACEX1K: Use logging feature instead of FPGA_DEBUG	Alexander Dahl	1	-21/+16
2022-10-10	fpga: cyclon2: Use logging feature instead of FPGA_DEBUG	Alexander Dahl	1	-22/+16
2022-10-10	fpga: altera: Use logging feature instead of FPGA_DEBUG	Alexander Dahl	1	-7/+4
2022-10-10	fpga: virtex2: Fix printf format string warnings	Alexander Dahl	1	-2/+2
2022-10-10	fpga: spartan3: Fix printf arguments warning	Alexander Dahl	1	-1/+1
2022-10-10	fpga: spartan2: Fix printf arguments warning	Alexander Dahl	1	-1/+1
2022-10-10	fpga: Add missing Kconfig symbols for old FPGA drivers	Alexander Dahl	1	-0/+12
2022-10-05	dm: fpga: Introduce new uclass	Alexander Dahl	4	-0/+50
2022-09-29	treewide: Drop image_header_t typedef	Simon Glass	1	-2/+2
2022-09-18	cyclic: Use schedule() instead of WATCHDOG_RESET()	Stefan Roese	2	-8/+8
2022-09-12	fpga: zynq: Remove post config info message for SPL	Stefan Herbrechtsmeier	1	-1/+2
2022-07-26	fpga: zynqmp: support loading encrypted bitfiles	Adrian Fiergolski	1	-0/+8
2022-07-26	fpga: zynqmp: support loading authenticated images	Oleksandr Suvorov	1	-5/+28
2022-07-26	fpga: zynqmp: add bitstream compatible checking	Oleksandr Suvorov	1	-0/+34
2022-07-26	fpga: zynqmp: reduce zynqmppl_load() code	Oleksandr Suvorov	1	-11/+6
2022-07-26	fpga: xilinx: pass compatible flags to load() callback	Oleksandr Suvorov	7	-7/+7
2022-07-26	fpga: add fpga_compatible2flag	Oleksandr Suvorov	1	-0/+26
2022-07-26	fpga: pass compatible flags to fpga_load()	Oleksandr Suvorov	2	-3/+4
2022-07-26	fpga: xilinx: pass compatible flags to xilinx_load()	Oleksandr Suvorov	2	-2/+2
2022-07-26	fpga: zynqmp: add str2flags call	Oleksandr Suvorov	1	-1/+10
2022-07-26	fpga: add option for loading FPGA secure bitstreams	Oleksandr Suvorov	4	-4/+18
2022-07-26	fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig	Alexander Dahl	3	-5/+7
2022-07-26	fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig	Alexander Dahl	2	-7/+6
2022-07-11	Merge branch 'next'	Tom Rini	1	-0/+6
2022-07-01	socfpga: arria10: Wait for fifo empty after writing bitstream	Paweł Anikiel	1	-0/+8
2022-07-01	socfpga: arria10: Improve bitstream loading speed	Paweł Anikiel	1	-2/+18
2022-06-29	Convert CONFIG_FPGA_STRATIX_V to Kconfig	Tom Rini	1	-0/+6
2021-12-17	arm: socfpga: arria10: Enable double peripheral RBF configuration	Tien Fong Chee	1	-1/+2
2021-09-30	WS cleanup: remove trailing empty lines	Wolfgang Denk	1	-1/+0
2021-03-08	arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64	Siew Chin Lim	1	-1/+1
2021-02-23	Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodia...	Tom Rini	1	-1/+1
2021-02-23	fpga: zynqpl: fix buffer alignment	Michael Walle	1	-1/+1
2021-02-16	image: Adjust the workings of fit_check_format()	Simon Glass	1	-3/+3
2021-02-02	common: Drop asm/global_data.h from common header	Simon Glass	2	-0/+2
2021-01-15	arm: socfpga: soc64: Add ATF support for FPGA reconfig driver	Chee Hong Ang	1	-0/+139
2020-10-09	arm: socfpga: agilex: Enable FPGA Full Reconfiguration support	Chee Hong Ang	1	-1/+1
2020-10-09	fpga: intel_sdm_mb: Add watchdog reset	Chee Hong Ang	1	-0/+3
2020-10-09	fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox	Chee Hong Ang	4	-11/+12
2020-09-23	fpga: zynqmp: Protect zynqmp_loads() for SPL	Michal Simek	1	-1/+1
2020-09-23	fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macros	Michal Simek	1	-4/+4
2020-08-20	xilinx: zynqmp: synchronize firmware call return payload	Ibai Erkiaga	1	-1/+1
2020-08-04	fs: fs-loader: Drop dm.h header file	Simon Glass	1	-0/+1
2020-06-24	arm64: xilinx: Print fpga error value in hex	T Karthik Reddy	2	-2/+2
2020-06-24	fpga: zynqpl: Flush dcache only for non-bitstream data	T Karthik Reddy	1	-2/+3
2020-06-24	fpga: zynqpl: Check if aes engine is enabled	Ibai Erkiaga	1	-0/+8
2020-06-24	fpga: zynqpl: Check fpga config completion	T Karthik Reddy	1	-2/+17
2020-06-24	fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes	Siva Durga Prasad Paladugu	1	-3/+4