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2020-05-19common: Drop net.h from common headerSimon Glass6-0/+6
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-15rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRATrevor Woerner1-1/+1
Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-14Merge tag 'u-boot-stm32-20200514' of ↵Tom Rini1-1/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - stm32mp1: migrate MTD and DFU configuration in Kconfig - stm32mp1: add command stm32prog - stm32mp1: several board and arch updates - stm32mp1: activate data cache in SPL and before relocation - Many improvment for AV96 board and DHCOR SoM (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM) - clk: stm32mp1: fix CK_MPU calculation - DT alignment of stm32mp1 device tree with Linux 5.7-rc2
2020-05-14mmc: stm32_sdmmc2: change the displayed config namePatrick Delaunay1-1/+1
Change the mmc displayed name in U-Boot for stm32_sdmmc2 driver to “STM32 SD/MMC”. This stm32_sdmmc2 driver is for version 2 of the ST HW IP SDMMC but the displayed name "STM32 SDMMC2" is confusing for user, between the instance of SDMMC and the device identifier of MMC. For example on EV1 board, we have: STM32MP1> mmc list STM32 SDMMC2: 0 (SD) STM32 SDMMC2: 1 (eMMC) Changed to more clear: STM32MP1> mmc list STM32 SD/MMC: 0 (SD) STM32 SD/MMC: 1 (eMMC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-13mmc: sdhci: Use debug for not supported SDMA info messageMatthias Brugger1-2/+2
If CONFIG_MMC_SDHCI_SDMA is enabled but the HW could not support it, we no longer error out. Instead we do not enable it in the host. Change the output from printf to debug as this isn't an error but only additional information now. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-12mmc: sdhci: not return error when SDMA is not supportedJaehoon Chung1-4/+3
If Host controller doesn't support SDMA, it doesn't need to return error. Because it can be worked with PIO mode. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-12mmc: sdhci: use phys2bus macro when dma address is accessedJaehoon Chung1-2/+4
Use phys2bus macro when dma address is accessed. Some targets need to use pyhs2bus macro. (e.g, RPI4) After applied it, SDMA mode can be used. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-04-27mmc: zynq: parse dt when probingBenedikt Grassl2-11/+7
Currently, the entry "bus-width = <8>" in the ZynqMP's sdhci nodes is not evaluated. This results in the bus width staying at its default value (4 bit in HS200 mode). Fix this by calling mmc_of_parse. This function also checks for the "no-1-8-v" and "max-frequency" entries. Remove the handling of those nodes from this driver. Signed-off-by: Benedikt Grassl <Benedikt.Grassl@rohde-schwarz.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-24dm: mmc: Update mmc_get_mmc_dev() to use const *Simon Glass1-1/+1
This function does not modify the device to change it to use const *, so that callers with a const udevice * can call it without a cast. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-22drivers: mmc: rpmb: do not build for SPLHeinrich Schuchardt1-1/+1
RPMB support is used by the 'mmc rpmb' command and by the OP-TEE support. We do not need it in SPL. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-04-22mmc: tmio: sdhi: Implement get_b_max functionMarek Vasut2-10/+37
Implement get_b_max() for the Renesas R-Car SDHI controller driver, limit the b_max per hardware capabilities such that select Gen2 controllers have 16bit block transfer limit, the rest has 32bit block transfer limit and on Gen3, the block transfer limit on addresses above the 32bit boundary is set to 1/4 of the malloc area. Originally, on Gen3, the block transfers above the 32bit area were limited to PIO only, which resulted in (R8A7795 Salvator-X , HS200 eMMC): => time mmc read 0x0000000700000000 0 0x10000 time: 0.151 seconds => time mmc read 0x0000000700000000 0 0x100000 time: 11.090 seconds with bounce buffer in place and b_max adjustment in place: => time mmc read 0x0000000700000000 0 0x10000 time: 0.156 seconds => time mmc read 0x0000000700000000 0 0x100000 time: 2.349 seconds Note that the bounce buffer does mallocate and free the bounce buffer for every transfer. Experiment which removes this results in further increase of read speed, from 2.349s to 2.156s per 512 MiB of data, which is not such a significant improvement anymore. It might however be interesting to have bounce buffer directly in the MMC core or even block core. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2020-04-22mmc: Add option to adjust b_max before long readMarek Vasut2-2/+30
Add getter function which permits adjusting the maximum number of blocks that could be read in a single sustained read transfer based on the location of the source/target buffer and length, before such transfer starts. This is mainly useful on systems which have various DMA restrictions for different memory locations, e.g. DMA limited to 32bit addresses, and where a bounce buffer is used to work around such restrictions. Since the U-Boot bounce buffer is mallocated, it's size is limited by the malloc area size, and the read transfer to such a buffer must also be limited. However, as not all areas are limited equally, the b_max should be adjusted accordinly as needed to avoid degrading performance unnecessarily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2020-04-22mmc: tmio: sdhi: Use bounce buffer to avoid DMA limitationsMarek Vasut2-0/+78
The R-Car SDHI DMA controller has various restrictions. To work around those restrictions without falling back to PIO, implement bounce buffer with custom alignment check function which tests for those limitations. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2020-04-22drivers: mmc: iproc_sdhci: move host.mmc init before sdhci_setup_cfgRayagonda Kokatanur1-5/+5
move host.mmc before sdhci_setup_cfg Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
2020-04-22drivers: mmc: iproc_sdhci: fix compilation warningRayagonda Kokatanur1-1/+3
set_ios_post return type changed from void to int, correcting the same to fix compilation warning. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
2020-04-22drivers: mmc: iproc_sdhci: enable broken R1B response quirkBharat Kumar Reddy Gooty1-1/+1
Enable SDHCI_QUIRK_BROKEN_R1B quirk. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-04-22drivers: mmc: iproc_sdhci: fix possible memory leakBharat Kumar Reddy Gooty1-3/+5
Free the pointer variable 'iproc_sdhci' upon failure to fix possible memory leak. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-04-22cmd: mmc: provide boot area protection commandHeinrich Schuchardt1-0/+5
Provide command 'mmc wp' to power on write protect boot areas on eMMC devices. The B_PWR_WP_EN bit in the extended CSD register BOOT_WP is set. The boot area are write protected until the next power cycle occurs. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-22mmc: export mmc_send_ext_csd()Heinrich Schuchardt1-1/+1
Export function mmc_send_ext_csd() for reading the extended CSD register. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-21mmc: tmio: sdhi: Add DMA transfer address alignment check at writingHiroyuki Yokoyama1-3/+5
In R-Car Gen 3, there is a DMA controller restriction of SDHI. When the transfer exceeding the 4 kByte boundary is performed while the DRAM address is not 128 byte aligned, the bus is occupied. This patch avoids this. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-04-06mmc: meson-gx: enable input clocksJerome Brunet1-1/+13
Until now, the mmc clock was left in a good enough state by the ROM code to be used by the controller. However on some SoC, if the ROM code finds a bootloader on USB or SPI, it might leave the MMC clock in state the controller cannot work with. Enable the input clocks provided to the mmc controller. While the u-boot mmc controller driver is not doing fancy settings like the Linux, it at least needs to make these clocks are running. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-03mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detectTom Warren1-0/+19
According to the HW team, for some reason the normal clock select code picks what appears to be a perfectly valid 375KHz SD card clock, based on the CAR clock source and SDMMC1 controller register settings (CAR = 408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register divisor of 16 = 375KHz). But the resulting SD card clock, as measured by the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on T210 when the requested clock is <= 400KHz. Note that as far as I can tell, the other requests for clocks in the Tegra MMC driver result in valid SD clocks. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-03mmc: t210: Add autocal and tap/trim updates for SDMMC1/3Tom Warren1-8/+76
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and autocal values need to be set to condition the signals correctly before talking to the SD-card. This is the same as what's being done in CBoot, but it gets reset when the SDMMC1 HW is soft-reset during SD driver init, so needs to be repeated here. Also set autocal and tap/trim for SDMMC3, although no T210 boards use it for SD-card at this time. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-03-09mmc: am654_sdhci: Implement workaround for card detectFaiz Abbas1-41/+68
The 4 bit MMC controllers have an internal debounce for the SDCD line with a debounce delay of 1 second. Therefore, after clocks to the IP are enabled, software has to wait for this time before it can power on the controller. Add a deferred_probe() callback which polls on sdcd for a maximum of 2 seconds before switching on power to the controller or (in the case of no card) returning a ENOMEDIUM. This pushes the 1 second wait time to when the card is actually needed rather than at every probe() making sure that users who don't insert an SD card in the slot don't have to wait such a long time. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09mmc: am654_sdhci: Update output tap delay writesFaiz Abbas1-9/+61
With the latest RIOT, there is a different otap delay value for each speed mode. Add a new binding with every supported speed mode. Also disable a given speed mode in the host caps if its corresponding otap-del-sel is not present. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09mmc: Merge SD_LEGACY and MMC_LEGACY bus modesFaiz Abbas4-12/+7
MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and don't have any meaningful differences. Therefore, get rid of all references to SD_LEGACY and use MMC_LEGACY to mean both of them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09sdhci: Add sdhci_deferred_probe() APIFaiz Abbas1-0/+15
Add the sdhci_deferred_probe() function to register as the deferred_probe() callback to the mmc core. It will in turn call the deferred_probe() callback of the platform drivers as declared in the sdhci_ops. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-03-09mmc: Add a deferred_probe() APIFaiz Abbas2-1/+18
Add a deferred_probe() API for platforms that want to do some configurations just before starting to enumerate the device. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-03-09mmc: ca_dw_mmc: add DesignWare based DM support for CAxxxx SoCsArthur Li3-0/+193
Initial DesignWare based DM support for Cortina Access CAxxxx SoCs. Signed-off-by: Arthur Li <arthur.li@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
2020-02-20mmc: sdhci: fix missing cache invalidation after reading by DMAMasahiro Yamada1-0/+4
This driver currently performs cache operation before the DMA start, but does nothing after the DMA completion. When reading data by DMA, the cache invalidation is needed also after finishing the DMA transfer. Otherwise, the CPU might read data from the cache instead of from the main memory when speculative memory read or memory prefetch occurs. Instead of calling the cache operation directly, this commit adds dma_unmap_single(), which performs cache invalidation internally, but drivers do not need which operation is being run. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-20mmc: sdhci: use dma_map_single() instead of flush_cache() before DMAMasahiro Yamada1-26/+25
Currently, sdhci_prepare_dma() calls flush_cache() regardless of the DMA direction. Actually, cache invalidation is enough when reading data from the device. This is correctly handled by dma_map_single(), which mimics the DMA-API in Linux kernel. Drivers can be agnostic which cache operation occurs behind the scene. This commit also sanitizes the difference between the virtual address and the dma address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-20mmc: sdhci: remove unneeded castsMasahiro Yamada1-3/+2
host->mmc is already (struct mmc *). memalign() returns an opaque pointer, so there is no need for casting. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-20mmc: sdhci: use lower_32_bit2() and upper_32_bits() for setting adma_addrMasahiro Yamada1-2/+3
Use {lower,upper}_32_bits() instead of the combination of cast and shift. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-20mmc: sdhci: reduce code duplication for aligned bufferMasahiro Yamada1-14/+8
The same code is run for both SDHCI_QUIRK_32BIT_DMA_ADDR and define(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER). Unify the code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-20mmc: sdhci: put the aligned buffer pointer to struct sdhci_hostMasahiro Yamada1-14/+13
Using the global variable does not look nice. Add a new field sthci::align_buffer to point to the bounce buffer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-19dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>Masahiro Yamada1-2/+1
The implementation of dma_map_single() and dma_unmap_single() is exactly the same for all the architectures that support them. Factor them out to <linux/dma-mapping.h>, and make all drivers to include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>. If we need to differentiate them for some architectures, we can move the generic definitions to <asm-generic/dma-mapping.h>. Add some comments to the helpers. The concept is quite similar to the DMA-API of Linux kernel. Drivers are agnostic about what is going on behind the scene. Just call dma_map_single() before the DMA, and dma_unmap_single() after it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19dma-mapping: fix the prototype of dma_unmap_single()Masahiro Yamada1-1/+1
dma_unmap_single() takes the dma address, not virtual address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19mmc: fsl_esdhc: actually enable cache snooping on mpc830xRasmus Villemoes1-2/+13
The reference manuals for MPC8308 and MPC8309 both say that the esdhcctl aka DMA Control Register "is implemented as SDHCCR" in the System configuration registers. Unfortunately, that doesn't mean that the registers are just mirrors of each other - any write to esdhcctl is simply ignored. So to actually enable cache snooping, we unfortunately have to add a little ifdeffery. There is, naturally, no description of the bit fields of esdhcctl in the MPC8309 manual, but comparing the description of esdhcctl from the LS1021A reference manual to the description of the sdhccr in MPC8309, one also finds that the fields are bit-reversed, so the bit to set is 0x02000000 rather than 0x00000040 - this is also what board_mmc_init() uses in the two gdsys/mpc8308/ boards. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-02-17mmc: remove unneeded forward declarationsMasahiro Yamada1-4/+0
These functions are defined before the callers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-02-17mmc: check the return value of mmc_select_mode_and_width()Masahiro Yamada1-1/+1
Since commit 01298da31d92 ("mmc: Change mode when switching to a boot partition"), errors in mmc_select_mode_and_width() are ignored. The return value should be checked. Fixes: 01298da31d92 ("mmc: Change mode when switching to a boot partition") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-17mmc: sdhci-cadence: send tune request twice to work around errataMasahiro Yamada1-4/+17
Cadence sent out an errata report to their customers of this IP. This errata is not so severe, but the tune request should be sent twice to avoid the potential issue. Quote from the report: Problem Summary --------------- The IP6116 SD/eMMC PHY design has a timing issue on receive data path. This issue may lead to an incorrect values of read/write pointers of the synchronization FIFO. Such a situation can happen at the SDR104 and HS200 tuning procedure when the PHY is requested to change a phase of sampling clock when moving to the next tuning iteration. Workarounds ----------- The following are valid workarounds to resolve the issue: 1. In eMMC mode, software sends tune request twice instead of once at each iteration. This means that the clock phase is not changed on the second request so there is no potential for clock instability. 2. In SD mode, software must not use the hardware tuning and instead perform an almost identical procedure to eMMC, using the HRS34 Tune Force register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-17mmc: fix the build error when MMC_WRITE is disabledJaehoon Chung1-0/+2
erase_grp_size is used, when MMC_WRITE is enabled. - error: ‘struct mmc’ has no member named ‘erase_grp_size’ Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-02-17drivers: mmc: rpmb: Use R1 responseBharat Kumar Reddy Gooty1-0/+5
If the host has Broken R1B, use only R1 response type. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
2020-02-06dm: core: Create a new header file for 'compat' featuresSimon Glass19-0/+22
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-06dm: core: Require users of devres to include the headerSimon Glass7-0/+8
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-01-29Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsungTom Rini1-0/+5
- Various exynos fixes
2020-01-25mmc: tmio-common: Drop custom dma mapping functionsVignesh Raghavendra1-22/+3
Drop local dma_map_single() and dma_unmap_single() and use arch specific common implementation Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-23mmc: s5p_sdhci: Read generic MMC properties from DTMarek Szyprowski1-0/+5
Read generic MMC properties from device-tree. This allows to specify for example cd-inverted property and let MMC core to properly handle such case. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-01-20Merge tag '2020-01-20-ti-2020.04' of ↵Tom Rini1-30/+99
https://gitlab.denx.de/u-boot/custodians/u-boot-ti K3 J721E: * DMA support. * MMC and ADMA support. * EEPROM support. * J721e High Security EVM support. * USB DT nodes K3 AM654: * Fixed boot due to pmic probe error. * USB support and DT nodes. * ADMA support DRA7xx/AM57xx: * BBAI board support * Clean up of net platform code under board/ti AM33/AM43/Davinci: * Reduce SPL size for omap3 boards. * SPL DT support for da850-lcdk * PLL divider fix for AM335x
2020-01-20mmc: am654_sdhci: Add Support for configuring PHY in J721eFaiz Abbas1-29/+98
Add Support for writing to PHY registers for J721e. There are number of differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY. Create a driver_data structure with an ops and flags field and use the flags field to indicate these differences. The differences are as follows: 1. The J721e 4 bit instance PHY does not have a DLL. Introduce a DLL_PRESENT flag to make sure that DLL related registers are accessed only where they are present. Also add a separate set_ios_post() callback. 2. The J721e 8 bit instance is not muxed with anything else inside the SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is used to indicate the presence of this field. 3. The register field used to select DLL frequency is 3 bit wide in J721e as compared to 2 bits in AM65x. Add another flag that distinguishes these fields. 4. The strobe select field is 8 bit wide as compared to 4 bit wide for AM65x. Add yet another flag to indicate this difference. Strobe select is used only for HS400 speed mode, support for which has not been added in AM65x. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-11 10:43:25 +0300