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2019-04-26mmc: mv_sdhci: add driver model supportPierre Bourdon1-1/+66
The new DM implementation currently does not support the Sheeva 88SV331xV5 specific quirk present in the legacy implementation. The legacy code is thus kept for this SoC and others not yet migrated to DM_MMC. Signed-off-by: Pierre Bourdon <delroth@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-24Merge tag 'u-boot-stm32-mcu-20190423' of https://github.com/pchotard/u-bootTom Rini3-13/+71
STM32 MCUs update: - DT rework and alignment with DT kernel v4.20 - mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20 - mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20 - configs: update for F746/769 boards
2019-04-24mmc: mtk-sd: fix configuration option checkFabien Parent1-4/+4
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO). IS_ENABLE(FOO) will always return false. This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO) syntax. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-04-24mmc: mtk-sd: add support for MT8516Fabien Parent1-0/+10
Add config for handling MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-24mmc: mtk-sd: add source_cg clock supportFabien Parent1-0/+5
Some MediaTek SoC need an additional clock "source_cg". Enable this new clock. We reuse the same clock name as in the kernel. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23mmc: stm32_sdmmc2: Fix r1b timeout issueChristophe Kerello1-6/+55
On response type r1b, if DTIME is not defined or too short, the Datatimeout and DPSM flag occurs. Like the DPSM is activated all next data transfer will be frozen. To avoid this freeze: -The driver must define a DTIME on all r1b response type. -DTIME of SDMMC must be defined for alls stop transmission (for read and write request) even if MMC_RSP_BUSY is not set. -If busy timeout occur, an abort request must be sent to reinitialize the DPSM. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2019-04-23mmc: stm32_sdmmc2: Update DT properties with v4.19 bindingsPatrick Delaunay1-3/+3
Some properties name has been updated: - st,dirpol becomes st,sig-dir - st,negedge becomes st,neg-edge - st,pin-ckin becomes st,use-ckin Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23mmc: arm_pl180_mmci: Sync compatible with kernelPatrice Chotard2-4/+13
Initially the compatible string was wrongly set to "st,stm32f4xx-sdio". Use compatible string used by kernel instead and identify mmci variant using "arm,primecell-periphid" property. Currently, the DM part of mmci driver is only used by STM32 SoCs, that's why the switch case gets only one entry. It will be populated easily with new variant in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-18ARC: dwmmc: Adding DesignWare MMC driver support for ARC devboardsEugeniy Paltsev3-0/+210
Add the DM_MMC-compatible DesignWare MMC driver support for Synopsys ARC devboards. It is created to switch ARC devboards to use DM_MMC. It required information such as clocks (Bus Interface Unit clock, Card Interface Unit clock) and SDIO bus width. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-04-12mmc: omap_hsmmc: Set 3.3V for IO voltageFaiz Abbas1-11/+10
Pbias voltage should match the IO voltage set for the SD card. With the latest pbias change to 3.3V, update the capabilities and IO voltages settings to 3.3V. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-03-29mmc: correct the HS400 initialization processBOUGH CHEN1-2/+1
After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed() which indicates that the HS200/HS400 to HS downgrade is happening. During the HS400 initialization, first select to HS200, and config the related clock rate, then downgrade to HS mode. So here also need to config the downgrade value to be true for two reasons. First, make sure in the function mmc_set_card_speed(), after switch to HS mode, first config the clock rate, then read the EXT_CSD, avoid receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue the MMC_CMD_SWITCH command, it need to wait a bit then switch bus properties. Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer mode in this case, and USDHC will never get data transfer complete status, cause the uboot hang. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2019-03-27Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2-2/+5
- Various fixes for bugs found by u-boot test.py
2019-03-25mmc: tmio: Clamp SD_SECCNT to 16bit values on 16bit IPMarek Vasut1-1/+4
On 16bit variants of the TMIO SD IP, the SECCNT register can only be programmed to 16bit values, while on the 32bit and 64bit variants it can be programmed to 32bit values. The SECCNT register indicates the maximum number of blocks in a continuous transfer. Hence, limit the maximum continuous transfer block count to 65535 blocks on 16bit variants of the TMIO IP and to BIT(32)-1 blocks on 32bit and 64bit variants. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-03-25mmc: sh_mmcif: Set default MMCIF clock rateMarek Vasut1-1/+1
Set MMCIF clock rate to 97.5 MHz, which is the default according to Gen2 datasheet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-03-25mmc: Align MMC_TRACE with tiny printfMarek Vasut1-10/+10
The tiny printf implementation only supports %x format specifier, it does not support %X . Since it makes little difference whether the debug output prints hex numbers in capitals or not, change it to %x and make the MMC_TRACE output work with tiny printf too. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org>
2019-02-25mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8Marek Vasut1-1/+1
According to latest specification rev.0026 and after confirmation with HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on H3 ES2.0 SoC. Make it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-25mmc: tmio: Clear BUSWIDTH bit when WMODE bit is setMarek Vasut1-1/+1
According to latest specification rev.0026, when HOST_MODE bit 0 (WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear HOST_MODE bit 8 in such case and align the code with Linux and avoid possible unforeseen issues. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-19Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini1-0/+19
- Misc Gen5 fixes - stratix10 bugfix - dwmmc bugfix
2019-02-18mmc: dwmmc: Poll for iDMAC TX/RX interruptLey Foon Tan1-0/+19
Poll for iDMAC TX/RX interrupt before disable DMA. This to prevent disable DMA before data is transfer completed. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-02-17Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini4-3/+55
- Various MMC fixes
2019-02-16mmc: tmio: sdhi: Configure DT2FF register for HS400 modeMarek Vasut1-0/+3
The DT2FF register must be configured differently for HS400 mode and for HS200/SDR104 mode. Configure the DT2FF register according to the recommended datasheet settings for each mode. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16mmc: tmio: Configure HOST_MODE WMODE according to bus widthMarek Vasut1-3/+7
Set the HOST_MODE register WMODE bit according to the SDHI bus width, that is 0 for 64bit bus and 1 for 16/32bit bus. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16mmc: Downgrade SD/MMC from UHS/HS200/HS400 modes before bootMarek Vasut2-0/+45
Older kernel versions or systems which do not connect eMMC reset line properly may not be able to handle situations where either the eMMC is left in HS200/HS400 mode or SD card in UHS modes by the bootloader and may misbehave. Downgrade the eMMC to HS/HS52 mode and/or SD card to non-UHS mode before booting the kernel to allow such older kernels to work with modern U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2019-02-16mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL buildsAbel Vesa1-4/+4
Since the fsl_esdhc will also be used by SPL, make the preprocessor switches more generic to allow any kind of build. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-10Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini5-13/+38
- SD/MMC fixes and ext4 memory leak fix
2019-02-10Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dmTom Rini2-58/+8
Samsung sound patches (applied for Samsung maintainer) Common sound support buildman environment support of-platdata documentation improvements
2019-02-09mmc: omap_hsmmc: Use regulator_set_enable_if_allowed for enabling regulatorLokesh Vutla1-8/+8
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable() while enabling io regulators. This way the driver doesn't see an error when disabling an always-on regulator and when enabling is not supported. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09samsung: mmc: Drop old MMC init codeSimon Glass1-50/+0
Now that these boards use driver model we can drop the old code. At present s5p_mmc_init() is still used by goni and smdkv310 so cannot be removed unless we remove those boards. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09mmc: omap_hsmmc: Workaround errata regarding SDR104/HS200 tuning failures (i929)Faiz Abbas1-1/+91
Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions (SPRZ426D - November 2014 - Revised February 2018 [1]) mentions unexpected tuning pattern errors. A small failure band may be present in the tuning range which may be missed by the current algorithm. Furthermore, the failure bands vary with temperature leading to different optimum tuning values for different temperatures. As suggested in the related Application Report (SPRACA9B - October 2017 - Revised July 2018 [2]), tuning should be done in two stages. In stage 1, assign the optimum ratio in the maximum pass window for the current temperature. In stage 2, if the chosen value is close to the small failure band, move away from it in the appropriate direction. References: [1] http://www.ti.com/lit/pdf/sprz426 [2] http://www.ti.com/lit/pdf/SPRACA9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-02-09mmc: Do not poll using CMD13 when changing timingMarek Vasut1-8/+20
When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy, do not poll for the completion status using CMD13, but rather wait 50mS. Once the card receives the CMD6 and starts executing it, the bus is in undefined state until both the card finishes executing the command and until the controller switches the bus to matching timing configuration. During this time, it is not possible to transport any commands or data across the bus, which includes the CMD13. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-02-09mmc: tmio: renesas: Add 1uS delay after DMA completion on older IPsMarek Vasut1-0/+3
The internal DMAC asserts DMA transfer end bit too early on older version of the TMIO IPs which use bit 17 for DTRAEND. Add 1uS delay after the completion of DMA transfer and before invalidating the cache to let the DMAC fully complete the transfer. Otherwise, it could happen that the last few bytes of a transferred data are not available. A test case to trigger this behavior is the following command, ran on the U-Boot command line, with Sandisk 16 GiB UHS-I card inserted into SDHI slot 0 and with first partition being of type FAT: => while true ; do mmc rescan ; fstype mmc 0:1 ; done Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-09mmc: tmio: Make DMA transfer end bit configurableMarek Vasut4-5/+15
Different versions of the SDHI core use either bit 17 or bit 20 for the DTRAEND indication, which can differ even between SoC revisions. Make the DTRAEND bit position part of the driver private data, so that the probe function can set this accordingly. Set this to 20 on Socionext SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-01-30Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini1-6/+47
- Enable DM_MMC support
2019-01-30Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imxTom Rini1-0/+1
For 2019.04
2019-01-29mmc: sunxi: Honour non-removable property in DTAndre Przywara1-1/+2
If a board DT describes a cd-gpios property, but also marks the storage as non-removable, we must ignore the GPIO (as Linux does). Teach the DM_MMC part of the Allwinner MMC driver about the non-removable DT property, to fix DM_MMC access on the SoPine and Pine64-LTS board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29mmc: sunxi: Add DM clk and reset supportAndre Przywara1-5/+13
Now that we have the gate clocks and the reset gates in our new Allwinner clock driver, let's make use of them in the MMC driver, when DM_MMC is defined. We treat the reset device as optional now, as the older SoCs don't implement it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29mmc: sunxi: Add DM_MMC support for A80Jagan Teki1-0/+8
A80 gates clock already be part of CLK framework, so just add mod_clk offset with A80 compatible string. Cc: Rask Ingemann Lambertsen <rask@formelder.dk> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29mmc: sunxi: Add DM_MMC support for H6Jagan Teki1-0/+12
Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset. Connect that with the respective compatible string. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29mmc: sunxi: Add remaining compatible stringsJagan Teki1-0/+12
Add MMC compatible strings for A83T, A64, H5. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-28mmc: fsl_esdhc: add compatible for fsl, imx53-esdhcPatrick Bruenn1-0/+1
Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms with CONFIG_DM_MMC=y Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2019-01-26drivers: esdhc: add support for ColdFire mcf5441x familyAngelo Dureghello1-1/+42
This patch has been tested on the mcf54415-based stmark2 board. The eSDHC driver works reliably using DMA mode. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2019-01-26mmc: mtk-sd: fix SPL compilation when GPIO=y and SPL_GPIO=nFabien Parent1-4/+4
It is not possible to link the SPL image when CONFIG_GPIO is enabled but CONFIG_SPL_GPIO is not. Use the IS_ENABLED macro instead to correctly check whether CONFIG_{SPL_}GPIO is enabled. This commit fixes the following errors: * undefined reference to `dm_gpio_get_value * undefined reference to `gpio_request_by_name' Signed-off-by: Fabien Parent <fparent@baylibre.com> [trini: Move guard to fix warning in msdc_ops_get_wp()] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-26mmc: mtk-sd: fix possible incomplete read opsFabien Parent1-9/+9
The code is checking for incomplete read when it see the INT_XFER_COMPL flag, but it forget to first check whether there is anything left in the FIFO to copy to the RX buffer. This means that sometimes we will get errors because of erroneous incomplete read operation. This commit fixes the driver re-ordering the code so that we first check for data inside the RX fifo and only after check the status of the INT_XFER_COMPL flag. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-01-25mmc: hi6220_dw_mmc: add compatible for Poplar supportShawn Guo1-0/+1
It adds compatible "hisilicon,hi3798cv200-dw-mshc" for Poplar SoC Hi3798CV200 to probe this mmc driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-24mmc: zynq: Remove unused pwrseq variableMichal Simek1-1/+0
This variable was incorrectly added by: "mmc: zynq_sdhci: Add support for SD3.0" (sha1: d1f4e39d58db32a4fd1a1b4085e0ede498bd773f) which had nothing to do with MMC power sequence provider. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-19Kconfig: Migrate BOUNCE_BUFFERPhilipp Tomsich1-0/+3
The bounce buffer is used by a few drivers (most of the MMC drivers) to overcome limitations in their respective DMA implementation. This moves the configuration to Kconfig and makes it user-selectable (even though it will be a required feature to make those drivers work): the expected usage is for drivers depending on this to 'select' it unconditionally from their respective Kconfig (see follow-up patches). This commit includes a full migration using moveconfig.py to ensure that each commit compiles. To ensure bisectability we update dependencies of various drivers to now select BOUNCE_BUFFER when needed. [trini: Squash all patches to ensure bisectability] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br> [dw_mmc portion] Reviewed-by: Fabio Estevam <festevam@gmail.com> [mxsmmc portion] Reviewed-by: Simon Glass <sjg@chromium.org> [tegra portion]
2019-01-19Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini1-1/+0
Add TFA boot flow for more boards Add TFA boot defconfig for ls1088a and ls2088a. Add dts fixup for PCIe endpoint and root complex.
2019-01-18Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mipsTom Rini2-48/+65
- MIPS: mscc: various enhancements for Luton and Ocelot platforms - MIPS: mscc: added support for Jaguar2 platform - MIPS: optimised SPL linker script - MIPS: bcm6368: fix restart flow issues - MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards - MIPS: mt7688: small fixes and enhancements - mmc: compile-out write support if disabled
2019-01-18mmc: fsl_esdhc: make get_cd work well in dm_mmc_opsYinbo Zhu1-1/+0
This patch is to make get_cd work well when DM_MMC enabled Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-16mmc: jz_mmc: Compile-out write support if disabledEzequiel Garcia1-44/+61
Do not build write support, unless it's enabled. In the SPL case, this change will typically remove precious bytes (as write support is most often not needed in SPL). This is important on this platform, where the maximum SPL size is 14 KiB. With gcc v7.3, this change saves 144 bytes producing: size spl/u-boot-spl text data bss dec hex filename 9240 752 712 10704 29d0 spl/u-boot-spl To make the code easier to compile-out and more readable, a pair of read_data/write_data helpers are created. Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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