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path: root/drivers/pci/Makefile
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2020-08-25pci: Add PCI controller driver for OcteonTX / TX2Suneel Garapati1-0/+1
Adds support for PCI ECAM/PEM controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-14drivers: pcie: add Broadcom IPROC PCIe RC driverSrinath Mannam1-0/+1
Add support for IPROC PAXC PCIe RC driver. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-27pci: layerscape: Add specific config entry for RC and EP mode driverHou Zhiqiang1-2/+5
Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci: layerscape: Split the EP and RC driverXiaowei Bao1-1/+1
Split the RC and EP driver, and reimplement the EP driver base on the EP framework. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-22pci: rockchip: Drop legacy PHY driverJagan Teki1-1/+1
Drop the legacy PHY driver and it's associated code since the PHY handling driver now part of Generic PHY framework. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-10pci: Add driver for Broadcom BCM2711 SoC PCIe controllerSylwester Nawrocki1-0/+1
This patch adds basic driver PCI Express controller found on Broadcom set-top-box SoCs, e.g. BCM2711. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 3GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-22pci: Add Rockchip PCIe PHY controller driverJagan Teki1-1/+1
Yes, it is possible to have a dedicated UCLASS PHY driver for this Rockchip PCIe PHY but there are some issues on Generic PHY framework to support the same. The Generic PHY framework is unable to get the PHY if the PHY parent is of a different uclass. Say if we try to get the PCIe PHY then the phy-uclass will look for PHY in the first instance if it is not in the root node it will try to probe the parent by assuming that the actual PHY is inside the parent PHY of UCLASS_PHY. But, in rk3399 hardware representation PHY like emmc, usb and pcie are part of syscon which is completely a different of UCLASS_SYSCON. Example: grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; pcie_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; }; Due to this limitation, this patch adds a separate PHY driver for Rockchip PCIe. This might be removed in future once Generic PHY supports this limitation. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22pci: Add Rockchip PCIe controller driverJagan Teki1-0/+1
Add Rockchip PCIe controller driver for rk3399 platform. Driver support Gen1 by operating as a Root complex. Thanks to Patrick for initial work. Signed-off-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
2020-01-24pci: layerscape: Common device tree fixup for NXP SoCsWasim Khan1-2/+3
Add Common device tree fixup for NXP SoCs. Based on SoC and revision call pcie_layerscape or pcie_layerscape_gen4 fixup. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26drivers/pci : enable pcie_layerscape code for lx2160a rev2Wasim Khan1-1/+1
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses pcie_layerscape driver. Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4. Based on SoC and revision pcie controller probe will be invoked. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-03pci: Only link pci_rom.o in some casesTom Rini1-2/+2
The content of pci_rom.c is only used in a few cases. Only build and link in these cases to avoid a global variable as gcc doesn't always discard those when they are unused. Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-08arm: add initial support for the Phytium Durian Boardliu hao1-0/+1
This adds platform code and the device tree for the Phytium Durian Board. The initial support comprises the UART and the PCIE. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-11-06pci: add DM based mpc85xx driverHeiko Schocher1-0/+1
add DM based PCI Configuration space access support for MPC85xx PCI Bridge. This driver is based on arch/powerpc/cpu/mpc85xx/pci.c In the old driver there is a fix for a hw issue on the TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I have no such hardware I did not port this part. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-11pci: mediatek: add PCIe controller support for MT7623Ryder Lee1-0/+1
This adds PCIe controller support for MT7623. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-08-12pcie: ti: add driver for AM65x PCIe RCSekhar Nori1-0/+1
Add driver supporting PCIe root-complex available on TI's AM65x SoC. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-06-20dm: pci: add Freescale PowerPC PCIe driverHou Zhiqiang1-0/+1
Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-27Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini1-0/+1
- Gen3 PCIe driver + enablement on Salvator-X platforms. - Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon. - SDHI HS400 fixes ported from latest BSP and datasheet.
2019-05-22pci: ls_pcie_g4: add device tree fixups for PCI Stream IDsHou Zhiqiang1-1/+2
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCsHou Zhiqiang1-0/+1
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-21pci: renesas: Add RCar Gen3 PCIe controller driverMarek Vasut1-0/+1
Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs. The PCIe on Gen3 is used both to connect external PCIe peripherals. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-08pci: intel: Add Intel FPGA PCIe controller driverLey Foon Tan1-0/+1
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in rootport mode only, the EP mode is not supported. The driver is tested with the Intel e1000e NIC driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-3/+1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-03-30arm64: a37xx: pci: add support for aardvark pcie driverWilson Ding1-0/+1
This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725 Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-27pci: rmobile: Add RCar Gen2 PCIe controller driverMarek Vasut1-0/+1
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs. The PCIe on Gen2 is used both to connect external PCIe peripherals as well as access the on-SoC USB EHCI controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-01-10PCI: Drop CONFIG_TSI108_PCITuomas Tynkkynen1-1/+0
Last user of this option went away in 2015 in commit: d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support") Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2017-10-06PCI: Add driver for a 'pci-host-ecam-generic' host controllerTuomas Tynkkynen1-0/+1
QEMU emulates such a device with '-machine virt,highmem=off' on ARM. The 'highmem=off' part is required for things to work as the PCI code in U-Boot doesn't seem to support 64-bit BARs. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-26Drop CONFIG_WINBOND_83C553Simon Glass1-1/+0
This is not used in U-Boot. Drop this option and associated dead code. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-18pci: layerscape: move kernel DT fixup to a separate fileHou Zhiqiang1-0/+1
To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-05pci: mvebu: Add PCIe driver for Armada-8KShadi Ammouri1-0/+1
This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core. The original version was written by Shadi and Yehuda. I ported this driver to the latest mainline U-Boot version with DM support. Tested on the Marvell DB-88F8040 Armada-8K eval board. Signed-off-by: Shadi Ammouri <shadi@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
2016-09-21pci: xilinx: Add a driver for Xilinx AXI to PCIe bridgePaul Burton1-0/+1
This patch adds a driver for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. This is mostly a case of implementing PCIe ECAM specification, but with some quirks about what devices are valid to access. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-12dm: pci: video: Convert video and pci_rom to use DM PCI APISimon Glass1-1/+2
Adjust these files to use the driver-model PCI API instead of the legacy functions. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12dm: pci: Use driver model PCI API in auto-configSimon Glass1-3/+3
At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01dm: pci: Disable PCI compatibility functions by defaultSimon Glass1-1/+2
We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01dm: pci: Move common auto-config functions to a common fileSimon Glass1-1/+1
Some functions will be used by driver model and legacy PCI code. To avoid duplication, put these in a separate, shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01dm: pci: Rename pci_auto.c to pci_auto_old.cSimon Glass1-1/+1
This file should not be used with driver model as it has lots of legacy/ compatibility functions. Rename it to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-17pci: mvebu: Add PCIe driverAnton Schubert1-0/+1
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the driver, this patch also removes the statically defined PCI MBUS windows. As they are not needed anymore, since this PCIe driver now creates the windows dynamically. Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000 PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp eval board using this Intel E1000 PCIe card in the PCIe 0 slot. This port was done in cooperation with Anton Schubert. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
2015-04-18dm: x86: pci: Add a PCI driver for driver modelSimon Glass1-0/+1
Add a simple x86 PCI driver which uses standard functions provided by the architecture. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-17dm: sandbox: pci: Add a PCI emulation uclassSimon Glass1-0/+1
Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-17dm: sandbox: Add a simple PCI driverSimon Glass1-0/+1
Add a driver which can access emulations of devices and make them available in sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-17dm: pci: Add a uclass for PCISimon Glass1-1/+7
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-17dm: pci: Move common PCI functions into their own fileSimon Glass1-1/+1
Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18pci: tegra: Add Tegra PCIe driverThierry Reding1-0/+1
Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes. This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-11arm: ls102xa: Update PCIe dts node statusMinghuan Lian1-0/+1
The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-25pci: Add general support for execution of video ROMsSimon Glass1-1/+1
Some platforms don't have native code for dealing with their video hardware. In some cases they use a binary blob to set it up and perform required actions like setting the video mode. This approach is a hangover from the old PC days where a ROM was provided and executed during startup. Even now, these ROMs are supplied as a way to set up video. It avoids the code for every video chip needing to be provided in the boot loader. But it makes the video much less flexible - e.g. it is not possible to do anything else while the video init is happening (including waiting hundreds of milliseconds for display panels to start up). In any case, to deal with this sad state of affairs, provide an API for execution of x86 video ROMs, either natively or through emulation. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-02-19Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD1-0/+1
2014-02-06ARM: PCI: Remove the IXP PCI driverMarek Vasut1-1/+0
The driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
2014-01-26ARM: mx6: Add PCI express driverMarek Vasut1-0/+1
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
2013-11-09malta: support for coreFPGA6 boardsPaul Burton1-0/+1
This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-10-31drivers: convert makefiles to Kbuild styleMasahiro Yamada1-33/+11
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-07-24MIPS: qemu-malta: add PCI supportGabor Juhos1-0/+1
Qemu emulates the Galileo GT64120 System Controller which provides a CPU bus to PCI bus bridge. The patch adds driver for this bridge and enables PCI support for the emulated Malta board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-01 07:34:12 +0300