summaryrefslogtreecommitdiff
path: root/drivers/pci/pci_auto.c
AgeCommit message (Collapse)AuthorFilesLines
2021-10-15pci: Fix configuring BARsPali Rohár1-6/+25
Number of BARs is defined by header type, not by class code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-15pci: Skip configuring PCI Rom Address for unsupported header typesPali Rohár1-1/+2
PCI Rom Address is currently supported only for Normal (0x00) and Bridge (0x01) header types. Fix code accordingly. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-03pci: include pci_internal.h inside pci_auto.cVladimir Oltean1-0/+1
To avoid a build warning with W=1, provide a function prototype for dm_pciauto_prescan_setup_bridge, which is a non-static function whose definition is inside pci_auto.c. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-23pci: Fix configuring io/memory base and limit registers of PCI bridgesPali Rohár1-10/+29
Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-08ppc: Remove caddy2 / vme8349 boardsTom Rini1-2/+1
These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-04-13pci: Mark 64bit Memory BARs as suchPhil Sutter1-1/+2
Just a bit more info to the reader. Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-28pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more)Stefan Roese1-63/+41
This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-27pci: Make auto-config code a little more robustPhil Sutter1-4/+5
On my DS414, some PCI devices return odd values when probing BAR sizes. An obvious case is all-ones response, the Linux driver (drivers/pci/probe.c) catches those explicitly and a comment explains that either bit 0 or bit 1 must be clear (depending on MEM or IO type). Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break size calculation due to the "middle" zeroes. Mitigate that copying more or less what Linux does and do a "find least bit set". Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-19pci: Update to use new sequence numbersSimon Glass1-5/+5
Now that we know the sequence number at bind time, there is no need for special-case code in dm_pci_hose_probe_bus(). Note: the PCI_CAP_ID_EA code may need a look, but there are no test failures so I have left it as is. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-19dm: Avoid accessing seq directlySimon Glass1-3/+3
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-08pci: Show a message if PCI autoconfig failsSimon Glass1-3/+9
At present this fails silently which can be confusing since some devices on the PCI bus may not work correctly. Show a message in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add a '\n' in the PCI autoconfig fail message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-20mpc83xx: Make distinct caddy2 configMario Six1-1/+2
vme8349.h contains two separate boards: The vme8349 itself, and the caddy2 board. The caddy2 board is chosen by setting certain config variables. Create a proper config file for the caddy2 board to make Kconfig migration easier. Furthermore, simplify the vme8349 and caddy2 configs by keeping only the options necessary for each board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20vme8349: Migrate to CONFIG_TARGET_VME8349Mario Six1-1/+1
CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Introduce ARCH_MPC834*Mario Six1-1/+1
Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-05-26PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resourcesTuomas Tynkkynen1-2/+4
Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-17dm: pci: change bus number register setting compliant with LinuxMinghuan Lian1-3/+3
This patch is to change U-Boot PCI bus assignement compliant with Linux. It means each PCIe controller's bus number is 0, not the current maximum PCI bus number, when start to scan this controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-26pci: Fix compiler warnings in dm_pciauto_setup_device()Bin Meng1-1/+1
Fix the following compiler warnings when DEBUG is on. warning: 'bar_res' may be used uninitialized in this function. drivers/pci/pci_auto.c:101:21: if (!enum_only && pciauto_region_allocate(bar_res, bar_size, ^ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-24dm: pci: Avoid using pci_bus_to_hose() in the uclassSimon Glass1-7/+7
This function is only available for compatibility with old code. Avoid using it in the uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-15dm: pci: Add a 'fall through' commentSimon Glass1-0/+1
For this class it is intended to set up the PCI device, so add a comment to indicate this. This avoids a coverity warning. Reported-by: Coverity (CID: 134194) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-12dm: pci: Use driver model PCI API in auto-configSimon Glass1-0/+386
At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01dm: pci: Rename pci_auto.c to pci_auto_old.cSimon Glass1-561/+0
This file should not be used with driver model as it has lots of legacy/ compatibility functions. Rename it to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21pci: Set PCI_COMMAND_IO bit for VGA deviceBin Meng1-0/+6
PCI_COMMAND_IO bit must be set for VGA device as it needs to respond to legacy VGA IO address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-08pci: Fix expansion ROM programming for multi-function devicesBin Meng1-0/+1
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05pci: Indicate prefetchable memory allocate when debuggingSimon Glass1-2/+3
At present the PCI output displays 'Mem' when it allocates memory for a PCI device, whether it is prefetchable or not. There is a distinction since the memory comes from separate pools. Use 'Prf' instead of 'Mem' when allocating prefetchable memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05pci: Fix up code for CONFIG_PCI_ENUM_ONLYSimon Glass1-1/+3
This option is not used by any board but appears to still be useful, at least for testing. With recent commits it does not build, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05pci: Use debug() instead of DEBUGF() in pci_auto.cSimon Glass1-25/+23
This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28dm: pci: Support bridge device configuration correctlyBin Meng1-12/+54
Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28dm: pci: Correct primary/secondary/subordinate bus number assignmentBin Meng1-0/+9
In driver model, each pci bridge device has its own hose structure. hose->first_busno points to the bridge device's device number, so we should not substract hose->first_busno before programming the bridge device's primary/secondary/subordinate bus number registers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-15pci: Configure expansion ROM during auto config processBin Meng1-26/+22
Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04pci: Do not skip legacy IDE device configurationBin Meng1-14/+0
The legacy IDE device has a BAR4 (Bus Master Interface BAR) which needs to be configured. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04pci: Allow debug message output in pci_auto.cBin Meng1-1/+0
Remove the '#undef DEBUG' in pci_auto.c so that we can enable debug message output via '-DDEBUG'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-17dm: pci: Add a uclass for PCISimon Glass1-3/+13
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-16PCI: add 64-bit prefetchable memory supportDavid Feng1-1/+35
PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-24x86: Access the VGA ROM when neededSimon Glass1-1/+27
Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-23linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada1-1/+1
U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-10-07pci: Properly configure prefetchable memory regionThierry Reding1-1/+1
Forcibly set hose->pci_prefetch to NULL to make sure it will be setup. This will help if for any reason callers didn't make sure themselves to NULL the field. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk1-4/+1
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2012-09-22pci: fix some warnings related to assumptions aboutKumar Gala1-1/+1
The following commit introduced some warnings associated with using pci_addr_t instead of a proper 32-bit data type. commit af778c6d9e2b945ee03cbc53bb976238a3374f33 Author: Andrew Sharp <andywyse6@gmail.com> Date: Wed Aug 1 12:27:16 2012 +0000 pci: fix errant data types and corresponding access functions On some platforms pci_addr_t is defined as a 64-bit data type so its not proper to use with pci_{read,write}_config_dword. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-09-02pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup doneAndrew Sharp1-10/+25
Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-09-02pci: clean up some whitespace and formattingAndrew Sharp1-20/+34
I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-09-02pci: fix errant data types and corresponding access functionsAndrew Sharp1-7/+8
In a couple of places, unsigned int and pci_config_*_dword were being used when u16 and _word should be used. Unsigned int was also being used in a couple of places that should be pci_addr_t. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2010-04-22Move arch/ppc to arch/powerpcStefan Roese1-1/+1
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
2009-07-28mpc83xx: Add esd VME8349 board supportReinhard Arlt1-1/+1
This patch adds support for the esd VME8349 board equipped with the MPC8349. It's a VME PMC carrier board equipped with the Tundra TSI148 VME-bridge. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-06-1283xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]xPeter Tyser1-1/+1
Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-25pci: Allow for PCI addresses to be 64-bitKumar Gala1-36/+52
PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD1-4/+4
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-13drivers/pci: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD1-4/+0
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-04-14Update CONFIG_PCIAUTO_SKIP_HOST_BRIDGE to related boardsTsiChung Liew1-1/+1
Remove test for CONFIG_MPC5200 in drivers/pci/pci_auto.c and define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE in related board configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-11 22:25:26 +0300