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path: root/drivers/pci/pcie_intel_fpga.c
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2020-12-14dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass1-2/+2
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass1-1/+1
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-09pci: Move some PCIe register offset definitions to a common headerSylwester Nawrocki1-3/+0
Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop linux/delay.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-06dm: core: Create a new header file for 'compat' featuresSimon Glass1-0/+1
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-06dm: pci: Update the PCI read_config() method to const dev *Simon Glass1-2/+2
At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11pci: intel: Fix configuration type based on secondary numberLey Foon Tan1-4/+6
This fix issue when access config from PCIe switch. The PCIe controller need to send Type 0 config TLP if the targeting bus matches with the secondary bus number, which is when the TLP is targeting the immediate device on the link. The PCIe controller send Type 1 config TLP if the targeting bus is larger than the secondary bus, which is when the TLP is targeting the device not immediate on the link. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11pci: intel: Fix error when enumerating multi-function PCIe deviceLey Foon Tan1-2/+4
Hardware return completion status non-zero when read from non exist function in multi-function PCIe device. Return error will cause PCIe enumeration fail. Change it to return 0 and return value 0xffffffff when error. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11pci: intel: Increase TLP polling counterLey Foon Tan1-1/+1
Some PCIe devices require longer time to response. Increase polling counter to 20000 (~100ms). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-08pci: intel: Add Intel FPGA PCIe controller driverLey Foon Tan1-0/+430
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in rootport mode only, the EP mode is not supported. The driver is tested with the Intel e1000e NIC driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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