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path: root/drivers/pci
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2021-07-19pci: Require DM_PCITom Rini4-983/+5
As the migration deadline has passed, require that DM_PCI be used. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18pci: msc01: convert to driver modelDaniel Schwierzeck1-1/+71
This driver is currently only used on MIPS Malta boards. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-18pci: gt64120: convert to driver modelDaniel Schwierzeck1-1/+73
This driver is currently only used on MIPS Malta boards. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-18dm: pci: add option to map virtual system memory base addressDaniel Schwierzeck2-3/+19
On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE is still used as a virtual, CPU-mapped address instead of being used as physical address. Converting all MIPS boards and generic MIPS code to fix that is not trivial. Due to the approaching deadline for PCI DM conversion, this workaround is required for MIPS boards with PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved. Add a compile-time option to let the PCI uclass core optionally map the DRAM address to a physical address when adding the PCI region of type PCI_REGION_SYS_MEMORY. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵Tom Rini1-5/+24
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-15Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini1-4/+35
- x86: various improvements made in getting Chromium OS verified boot running on top of coreboot, booting into U-Boot.
2021-07-15x86: pci: Allow binding of some devices before relocationSimon Glass1-1/+32
At present only bridge devices are bound before relocation, to save space in pre-relocation memory. In some cases we do actually want to bind a device, e.g. because it provides the console UART. Add a devicetree binding to support this. Use the PCI_VENDEV() macro to encode the cell value. This is present in U-Boot but not used, so move it to the binding header-file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15pci: Use const for pci_find_device_id() etc.Simon Glass1-3/+3
These functions don't modify the device-ID struct that is passed in, so mark the argument as const, so the data structure can be declared that way. This allows it to be placed in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15arm: a37xx: pci: Fix typo in commentPali Rohár1-1/+1
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-15arm: a37xx: pci: Extend validation for PCIe resources and oubound windowsPali Rohár1-3/+4
Remapped address of PCIe outbound window may have set only bits from the mask. Add additional check that remapped address which is calculated from PCIe bus address specified in DTS file is valid. Remove also useless clearing of low 16 bits in win_mask. As win_size is power of two and is at least 0x10000 it means that it always has zero low 16 bits. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-14pci: uniphier: Add UniPhier PCIe controller driverKunihiko Hayashi3-0/+435
Add PCIe driver for UniPhier SoCs. This PCIe controller is based on Synopsys DesignWare Core IP. This version doesn't apply common DW functions because supported controller doesn't have unroll version of iATU. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-10pci: imx: use reset-gpios if defined by device-treeTim Harvey1-5/+24
If reset-gpio is defined by device-tree use that if CONFIG_PCIE_IMX_PERST_GPIO is not defined. Note that after this the following boards which define CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without consequence: - mx6sabresd - mx6sxsabresd - novena - tbs2910 - vining_2000 Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_PERST_GPIO and does not have reset-gpios defined it it's pcie node in the dt thus removing CONFIG_PCIE_IMX_PERST_GPIO globally can't be done until that board adds reset-gpios. Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD) Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD) Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD) Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD) Cc: Soeren Moch <smoch@web.de> (maintainer:TBS2910 BOARD) Cc: Silvio Fricke <open-source@softing.de> (maintainer:VINING_2000 BOARD) Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-08ppc: Remove caddy2 / vme8349 boardsTom Rini1-2/+1
These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmTom Rini1-0/+2
various minor sandbox improvements
2021-07-06pci: synquacer: Add SynQuacer ECAM based PCIe driverMasami Hiramatsu3-0/+613
Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06dm: pci: Skip setting VGA bridge bits if parent device is the host busMasami Hiramatsu1-0/+3
Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges") sets the VGA bridge bits by checking pplat->class, but if the parent device is the pci host bus device, it can be skipped. Moreover, it shouldn't access the pplat because the parent has different plat data. Without this fix, "pci enum" command cause a synchronous abort. pci_auto_config_devices: start PCI Autoconfig: Bus Memory region: [78000000-7fffffff], Physical Memory [78000000-7fffffffx] PCI Autoconfig: Bus I/O region: [0-ffff], Physical Memory [77f00000-77f0ffffx] pci_auto_config_devices: device pci_6:0.0 PCI Autoconfig: BAR 0, Mem, size=0x1000000, address=0x78000000 bus_lower=0x79000000 PCI Autoconfig: BAR 1, Mem, size=0x8000000, No room in resource, avail start=79000000 / size=8000000, need=8000000 PCI: Failed autoconfig bar 14 PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004 PCI Autoconfig: BAR 3, Mem, size=0x2000000, address=0x7a000000 bus_lower=0x7c000000 PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100 PCI Autoconfig: ROM, size=0x80000, address=0x7c000000 bus_lower=0x7c080000 "Synchronous Abort" handler, esr 0x96000006 elr: 00000000e002bd28 lr : 00000000e002bce8 (reloc) elr: 00000000fff6fd28 lr : 00000000fff6fce8 x0 : 0000000000001041 x1 : 000000000000003e x2 : 00000000ffb0f8c8 x3 : 0000000000000001 x4 : 0000000000000080 x5 : 0000000000000000 x6 : 00000000fff718fc x7 : 000000000000000f x8 : 00000000ffb0f238 x9 : 0000000000000008 x10: 0000000000000000 x11: 0000000000000010 x12: 0000000000000006 x13: 000000000001869f x14: 00000000ffb0fcd0 x15: 0000000000000020 x16: 00000000fff71cc4 x17: 0000000000000000 x18: 00000000ffb13d90 x19: 00000000ffb14320 x20: 0000000000000000 x21: 00000000ffb14090 x22: 00000000ffb0f8c8 x23: 0000000000000001 x24: 00000000ffb14c10 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 00000000ffb14c70 x29: 00000000ffb0f830 Code: 52800843 52800061 52800e00 97ffcf65 (b9400280) Resetting CPU ... Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini1-0/+4
Prepare v2021.07-rc5 # gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # configs/am64x_evm_r5_defconfig
2021-06-18pci: pcie_dw_rockchip: Replace msleep occurences by udelayAnand Moon1-5/+5
Replace msleep occurences by udelay. drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit declaration of function 'msleep' [-Wimplicit-function-declaration] Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18pci: pcie_dw_rockchip: Drop the unused variable warningAnand Moon1-2/+0
Drop the unused variable warning below. drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable 'val' [-Wunused-variable] 161 | u32 val; | ^~~ Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18pci: pcie_dw_rockchip: Fixed the below compilation errorAnand Moon1-2/+2
Use the generic error number instead of specific error number. Changes fix the below error. drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read': drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 70 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write': drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 90 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-17pci: layerscape-ep: Add check of the PCIe controller enablementHou Zhiqiang1-0/+4
Stop to initialize the PCIe controller if it's disabled by RCW. Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-04arm: a37xx: pci: Fix configuring PCIe resourcesPali Rohár1-1/+157
The `ranges` DT property of the PCIe node is currently ignored by Aardvark driver - all entries are used as transparent PCIe MEM, despite some of them being defined for IO in DT. This is because the driver does not setup PCIe outbound windows and thus a default configuration is used. This can cause an external abort on CPU when a device driver tries to access non-MEM space. Setup the PCIe windows according to the `ranges` property for all non-MEM resources (currently only IO) and also non-transparent MEM resources. Because Linux expects that bootloader does not setup Aardvark PCIe windows, disable them before booting Linux. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-04arm: a37xx: pci: Fix DT compatible string to Linux' DT compatiblePali Rohár1-1/+1
Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie' to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible with Linux' DT node. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-04arm: a37xx: pci: Disable bus mastering when unloading driverPali Rohár1-0/+6
Disable Root Bridge I/O space, memory space and bus mastering in Aardvark's remove method, which is called before booting Linux kernel. This ensures that PCIe device which was initialized and used by U-Boot cannot do new DMA transfers until Linux initializes PCI subsystem and loads appropriate drivers for the device. During initialization of PCI subsystem Linux in fact disables this bus mastering on Root Bridge (and later enables it when driver is loaded and configured), but there is a possibility of a small window after U-Boot boots Linux when bus mastering is enabled, which is not correct. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-04arm: a37xx: pci: Don't put link into LTSSM Recovery state during probePali Rohár1-5/+0
During our debugging of the Aardvark driver in Linux we have discovered that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard PCIe Link Control Register for PCIe Root Bridge. This led us to discover that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding comment by this macro's usage is misleading; this bit in fact controls Retrain Link, which, according to PCIe base spec is defined as: A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. Entering Recovery state is normally done from LTSSM L0, L0s and L1 states. But since the pci-aardvark.c driver enables Link Training just a few lines above, the controller is not in L0 ready state yet. So setting aardvark bit PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this place. Moreover, trying to enter LTSSM Recovery state without other configuration is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since Recovery state is not entered, these issues are not triggered. Remove code which tries to enter LTSSM Recovery state completely. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-05-31drivers: pci: pcie_dw_common: fix Werror compilation errorGreen Wan1-25/+29
Fix compilation error when Werror is turned on. The warning could possible break some CI builds. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-05-31drivers: pci: add pcie support for fu740Green Wan3-0/+518
Add pcie driver for SiFive fu740, the driver depends on fu740 gpio, clk and reset driver to do init. Force running at Gen1 for better capatible enumeration. Several devices are tested: a) M.2 NVMe SSD b) USB-to-PCI adapter c) Ethernet adapter (E1000 compatible) Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-16pcie: designware: mvebu: do not configure ATU for IO when not usedMarcin Wojtas1-12/+25
The pcie_dw_mvebu configure ATU regions for memory, configuration and IO space types. However the latter is not obligatory and when not specified in the device tree, causes wrong ATU configuration. Fix that by adding a dependency on the detected PCIE regions count. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/18136 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2021-05-02pci: imx: disable imx6sdl LTSSM upon driver removeTim Harvey1-1/+1
commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function") attempted to resolve an issue caused by MX6QDL not having a proper intneral PCIe core reset and thus hanging during kernel init if the bootloader had enabled PCI. The issue exists for IMX6Q, IMX6D, IXM6S, and IMX6DL. Fix the case for IMX6S and IMX6DL getting missed. This fixes IMX6S and IMX6DL with PCI enabled in U-Boot booting for Linux v4.11+. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-05-02pci: pci-uclass: Add board_pci_fixup_dev for DM_PCITim Harvey1-0/+6
Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-05-02pci: Update the highest subordinate bus number for bridge setupMasami Hiramatsu1-0/+3
Update the highest subordinate bus number after probing the devices under the bus for setting up the bridge correctly. The commit 42f3663a3f67 ("pci: Update to use new sequence numbers") removed this but it is required if a PCIe bridge is under the bus. Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers") Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-04-29arm: a37xx: pci: Fix processing PIO transfersPali Rohár1-14/+28
Trying to clear PIO_START register when it is non-zero (which indicates that previous PIO transfer has not finished yet) causes an External Abort with SError 0xbf000002. This bug is currently worked around in TF-A by handling External Aborts in EL3 and ignoring this particular SError. This workaround was also discussed at: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 https://lore.kernel.org/linux-pci/20190316161243.29517-1-repk@triplefau.lt/ https://lore.kernel.org/linux-pci/971be151d24312cc533989a64bd454b4@www.loen.fr/ https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1541 Implement a proper fix to prevent this External Abort. As it is not possible to cancel a pending PIO transfer, simply do not start a new one if previous has not finished yet. In this case return an error to the caller. In most cases this SError happens when there is no PCIe card connected or when PCIe link is down. The reason is that in these cases a PIO transfer takes about 1.44 seconds. For this reason we also increase the wait timeout in pcie_advk_wait_pio() to 1.5 seconds. If PIO read transfer for PCI_VENDOR_ID register times out, or if it isn't possible to read it yet because previous transfer is not finished, return Completion Retry Status value instead of failing, to give the caller a chance to send a new read request. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-28mips: octeon: Add Octeon PCIe host controller driverStefan Roese3-0/+166
This patch adds the PCIe host controller driver for MIPS Octeon II/III. The driver mainly consist of the PCI config functions, as all of the complex serdes related port / lane setup, is done in the serdes / pcie code available in the "arch/mips/mach-octeon" directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-15pci: add Amlogic Meson Designware PCIe controllerNeil Armstrong3-0/+468
Add support for the DW PCIe controller found in the Amlogic Meson AXG and G12 (G12A, G12B, SM1) SoCs. This uses the common DW PCIe helpers introducted previously. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-15pci: pcie_dw_rockchip: migrate to common Designware PCIe functionsNeil Armstrong2-444/+30
Migrate the dw_rockchip driver to use the common DW PCIe helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-15pci: pcie_dw_ti: migrate to common Designware PCIe functionsNeil Armstrong2-408/+38
Migrate the dw_ti driver to use the common DW PCIe helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-15pci: add common Designware PCIe functionsNeil Armstrong4-0/+525
With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in the Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated. This introduce a "common" DW PCIe helpers file with common code merged from the dw_ti and dw_rockchip drivers and adapted to fit with the upcoming dw_meson. The following changes will switch the dw_ti and dw_rockchip to use these helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Green Wan <green.wan@sifive.com> [bmeng: remove the blank line at EOF of drivers/pci/pcie_dw_common.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-04-13pci: Mark 64bit Memory BARs as suchPhil Sutter1-1/+2
Just a bit more info to the reader. Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-30Merge tag 'v2021.04-rc5' into nextTom Rini2-2/+2
Prepare v2021.04-rc5
2021-03-27video: Fix video on coreboot with the copy bufferSimon Glass1-5/+2
The copy buffer, if enabled, prevents booting from coreboot correctly, since no memory is allocated for it. Allow it to fall back to disabled in this situation. This ensures that a console is displayed, even if it is slow. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-23pci: layerscape: Change to allocate zeroed memery for struct ls_pcieHou Zhiqiang2-2/+2
As on some incipient Layerscape platforms (LS1043A series) there isn't separate PF control register block, these registers reside in the LUT register block, so when the driver detected there isn't 'ctrl', it will assign the 'lut' address to the ls_pcie->ctrl. The current code allocate memory for the struct ls_pcie with random contents, this can result in skipping to assign the ls_pcie->ctrl with the 'lut' address, then further crash with the incorrect address. Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-12arm: a37xx: pci: Implement workaround for the readback value of VEND_IDPali Rohár1-0/+10
Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in U-Boot PCIe controller driver aardvark for both PCI vendor id and PCI subsystem vendor id. This change affects PCI vendor id of PCIe root bridge emulated by Linux kernel. With this change Linux kernel reports correct vendor id 11AB. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-05pci: mpc85xx: Support 64-bit bus and cpu addressBin Meng1-8/+8
At present the driver only supports 32-bit bus and cpu address. The controller's outbound registers/fields for extended address are not programmed. Let's program them to support 64-bit bus and cpu address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05pci: mpc85xx: Support controller register physical address beyond 32-bitBin Meng1-3/+2
devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit physical address. Use map_physmem() to return the virtual address that can be used by a 32-bit machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAWBin Meng1-0/+4
For the QEMU ppce500 machine, LAW registers are not implemented hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not available. We should wrap all LAW registers programming in the mpc85xx PCI driver with CONFIG_FSL_LAW. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-05pci: fsl_pci_init: Dynamically allocate the PCI regionsBin Meng1-0/+5
Commit e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") changes 'struct pci_controller'.regions from pre-allocated array of regions to dynamically allocated, which unfortunately broken lots of boards that still use the non-DM PCI driver. This patch changes the non-DM fsl_pci_init driver to dynamically allocate the regions, just like what's done in the pci uclass driver. Fixes: e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-26pci: pci_mvebu: set local dev to number 1Marek Behún1-1/+1
Linux displays the real PCIe card connected to a mvebu PCIe slot as device 0, not 1. This is done by setting local dev number to 1, so that the local "Marvell Memory controller" device is on address 1. Let's do it also in U-Boot. With this commit the pci command in U-Boot prints something like: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x168c 0x003c Network controller 0x80 Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26pci: pci_mvebu: refactor validation of addresses for config accessMarek Behún1-28/+31
Refactor validation of bdf parameter in mvebu_pcie_read/write_config functions. We can simplify the code by putting the validation into separate function. Also there are always only two devices visible on local bus: * on slot configured by function mvebu_pcie_set_local_dev_nr() (by default this register is set to 0) there is a "Marvell Memory controller", which isn't useful in root complex mode, * on all other slots the real PCIe card connected to the PCIe slot. We can simplify the code even more by simply allowing access only to the real PCIe card. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26pci: pci_mvebu: debug rd/wr config as other drivers doMarek Behún1-2/+2
Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when debugging is enabled. Print size for pci_mvebu as well. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
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