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path: root/drivers/pci
AgeCommit message (Expand)AuthorFilesLines
2022-01-20Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini3-13/+21
2022-01-20pci: pci_mvebu: Add support for Kirkwood PCIe controllersPali Rohár2-3/+19
2022-01-20fdt_support: Add fdt_for_each_node_by_compatible() helper macroMarek Behún1-10/+2
2022-01-19doc: replace @return by Return:Heinrich Schuchardt4-7/+7
2022-01-14pci: Work around PCIe link training failuresMaciej W. Rozycki1-0/+170
2022-01-14arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.cPali Rohár2-1/+43
2022-01-14pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe()Pali Rohár1-0/+23
2022-01-14pci: pci_mvebu: Split initialization of PCIe ports into 3 phasesPali Rohár1-22/+84
2022-01-14pci: pci_mvebu: Remove dependency on SOC_REGS_PHY_BASE macroPali Rohár1-2/+4
2022-01-14pci: pci_mvebu: Inline mvebu_pcie_port_parse_dt() functionPali Rohár1-18/+9
2022-01-14pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mappingPali Rohár1-25/+59
2022-01-12pci: sh7751: Fix access to config space via PCI_CONF1_ADDRESS() macroPali Rohár1-27/+2
2022-01-12pci: sh7780: Use PCI_CONF1_ADDRESS() macroPali Rohár1-4/+4
2022-01-12pci: mediatek: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-9/+8
2022-01-12pci: fsl: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-4/+6
2022-01-12pci: tegra: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-8/+3
2022-01-12pci: mvebu: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-13/+4
2022-01-12pci: msc01: Use PCI_CONF1_ADDRESS() macroPali Rohár1-5/+2
2022-01-12pci: mpc85xx: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-2/+2
2022-01-12pci: gt64120: Use PCI_CONF1_ADDRESS() macroPali Rohár1-5/+2
2022-01-12pci: When disabling pref MEM set all base bitsPali Rohár1-1/+1
2022-01-12pci: Disable I/O forwarding during autoconfiguration if unsupportedPali Rohár1-0/+8
2022-01-12pci: Fix register for determining type of IO base addressPali Rohár1-1/+1
2022-01-12pci: pci_octeontx: Use PCIE_ECAM_OFFSET() macroPali Rohár1-41/+20
2022-01-12pci: pcie_iproc: Use PCIE_ECAM_OFFSET() macroPali Rohár1-14/+3
2022-01-12pci: pcie-brcmstb: Use PCIE_ECAM_OFFSET() macroPali Rohár1-6/+1
2021-12-28Convert CONFIG_SYS_PCI_64BIT to KconfigTom Rini1-0/+6
2021-12-27pci: Remove unused FSL_PCI_INIT codeTom Rini2-937/+0
2021-12-21pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTRPali Rohár1-3/+0
2021-12-21pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size()Pali Rohár1-6/+6
2021-12-21pci: pci_mvebu: Move setup for BAR[0] where other BARs are setupPali Rohár1-5/+7
2021-12-21Merge tag 'v2022.01-rc4' into nextTom Rini2-48/+61
2021-12-19arm: mvebu: pci: Add me as co-maintainer and author of Marvell PCIe driversPali Rohár2-0/+2
2021-12-19fdt_support: Remove FDT_STATUS_FAIL_ERROR_CODEMarek Behún2-8/+8
2021-12-15arm: a37xx: pci: Do not allow setting ROM BAR on PCI BridgePali Rohár1-24/+30
2021-12-15pci: pci_mvebu: Do not allow setting ROM BAR on PCI BridgePali Rohár1-24/+31
2021-12-15pci: pci_mvebu, pci_aardvark: Fix size of configuration cacheMarek Behún2-2/+2
2021-11-18RFC: arm: pci: Add PCI cam support to PCI-E ecam driverAlistair Delva1-3/+12
2021-11-18pci: Add standard PCIe ECAM macrosPali Rohár6-41/+11
2021-11-11Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini5-26/+61
2021-11-10pci: pci_mvebu: Use global MBUS_PCI_MEM_SIZE macroPali Rohár1-6/+5
2021-11-09pci: layerscape: Fix the LUT and msi-map mismatch issueHou Zhiqiang5-10/+16
2021-11-09pci: layerscape: add official ls1028a binding supportMichael Walle1-16/+45
2021-11-03arm: a37xx: pci: Program the data strobe for config read requestsPali Rohár1-0/+3
2021-11-03pci: pci_mvebu: Fix comment about driver class namePali Rohár1-1/+1
2021-11-03pci: pci_mvebu: Setup PCI controller to Root Complex modePali Rohár1-0/+6
2021-11-03pci: pci_mvebu: Do not automatically enable bus mastering on PCI BridgePali Rohár1-8/+0
2021-11-03pci: pci_mvebu: Fix place of link up detectionPali Rohár1-10/+4
2021-11-03pci: pci_mvebu: Remove unused functionsPali Rohár1-16/+0
2021-11-03pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)Pali Rohár1-35/+164
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-22 22:16:43 +0300