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2020-08-14drivers: pcie: add Broadcom IPROC PCIe RC driverSrinath Mannam3-0/+1295
Add support for IPROC PAXC PCIe RC driver. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14drivers: pci: add api to get dma regionsRayagonda Kokatanur1-0/+42
Add api to get dma regions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-08-04pci: Drop dm.h inclusion from header fileSimon Glass4-2/+3
The layerscape header should not include dm.h so remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-27pci: layerscape: Add specific config entry for RC and EP mode driverHou Zhiqiang2-8/+28
Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2Xiaowei Bao2-2/+15
Add the PCIe EP mode support for lx2160a-v2 platform. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci: layerscape: Modify the ls_pcie_dump_atu functionXiaowei Bao4-14/+18
Modify the ls_pcie_dump_atu function, make it can print the INBOUND windows registers. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci_ep: layerscape: Add the SRIOV VFs of PF supportXiaowei Bao3-13/+42
Add the INBOUND configuration for VFs of PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci_ep: layerscape: Add Support for ls2085a and ls2080a EP modeXiaowei Bao1-5/+13
Due to the ls2085a and ls2080a use different way to set the BAR size, so add the BAR size init code here. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci_ep: layerscape: Add the workaround for errata A-009460Xiaowei Bao1-0/+9
The VF_BARn_REG register's Prefetchable and Type bit fields are overwritten by a write to VF's BAR Mask register. workaround: Before writing to the VF_BARn_MASK_REG register, write 0b to the PCIE_MISC_CONTROL_1_OFF register. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pcie_ep: layerscape: Add the multiple function supportXiaowei Bao3-48/+98
Add the multiple function support for Layerscape platform, some PEXs of Layerscaple platform have more than one PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27pci: layerscape: Split the EP and RC driverXiaowei Bao6-497/+735
Split the RC and EP driver, and reimplement the EP driver base on the EP framework. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-22pci: rockchip: Drop legacy PHY driverJagan Teki4-354/+74
Drop the legacy PHY driver and it's associated code since the PHY handling driver now part of Generic PHY framework. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22pci: rockchip: Switch to generic-phyJagan Teki3-10/+16
Now, we have a PCIe PHY driver as part of the Generic PHY framework. Let's use it instead of legacy PHY driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-17treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada6-10/+10
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-10Merge tag 'rpi-next-2020.10' of ↵Tom Rini5-11/+633
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - add support for PCI and XHCI for RPi4 (64 bit only) - optionally reset XHCI device on registration - enable USB_KEYBOARD for rpi_4_defconfig
2020-07-10pci: Add driver for Broadcom BCM2711 SoC PCIe controllerSylwester Nawrocki3-0/+633
This patch adds basic driver PCI Express controller found on Broadcom set-top-box SoCs, e.g. BCM2711. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 3GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-09pci: Move some PCIe register offset definitions to a common headerSylwester Nawrocki2-11/+0
Some PCI Express register offsets are currently defined in multiple drivers, move them to a common header to avoid re-definitions and as a pre-requisite for adding new PCIe driver. While at it replace some spaces with tabs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-09video: pci: Set up the copy framebufferSimon Glass1-1/+21
When using a copy framebuffer we need to tell the video subsystem its address. U-Boot's normally allocated framebuffer is used as the working buffer, but nothing is displayed until it is copied to the copy framebuffer. For this to work the video driver must request that a framebuffer be allocated separately from the hardware framebuffer, so add a check for that. Also add a log category so that logging appears correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01pci: rockchip: Mark inline functions as static inlineTom Rini1-3/+2
Unless we mark the function as 'static inline' it may end up being non-inlined by the compiled and result in duplicate functions. Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-05-29pci: Make Rockchip PCIe voltage regulators optionalMark Kettenis1-13/+20
The vpcie*-supply properties are optional and these are absent on boards like the ROCKPro64 and Firefly RK3399 where the voltage is supplied by always-on regulators that are already enabled upon boot. Make these regulators optional and properly check their presence before attempting to enable them. Makes PCIe work on un U-Boot on the boards mentioned above. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
2020-05-22pci: Add Rockchip PCIe PHY controller driverJagan Teki4-14/+306
Yes, it is possible to have a dedicated UCLASS PHY driver for this Rockchip PCIe PHY but there are some issues on Generic PHY framework to support the same. The Generic PHY framework is unable to get the PHY if the PHY parent is of a different uclass. Say if we try to get the PCIe PHY then the phy-uclass will look for PHY in the first instance if it is not in the root node it will try to probe the parent by assuming that the actual PHY is inside the parent PHY of UCLASS_PHY. But, in rk3399 hardware representation PHY like emmc, usb and pcie are part of syscon which is completely a different of UCLASS_SYSCON. Example: grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; pcie_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; }; Due to this limitation, this patch adds a separate PHY driver for Rockchip PCIe. This might be removed in future once Generic PHY supports this limitation. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22pci: Add Rockchip PCIe controller driverJagan Teki4-0/+555
Add Rockchip PCIe controller driver for rk3399 platform. Driver support Gen1 by operating as a Root complex. Thanks to Patrick for initial work. Signed-off-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass11-0/+11
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop linux/delay.h from common headerSimon Glass13-0/+13
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass22-0/+22
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop init.h from common headerSimon Glass7-0/+7
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop bootstage.h from common headerSimon Glass1-0/+1
Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-15rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRATrevor Woerner1-1/+1
Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-04-30pci: Avoid auto-config when chain loadingSimon Glass1-2/+2
When U-Boot is not the first-stage bootloader we don't want to re-configure the PCI devices, since this has already been done. Add a check to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-16x86: Move acpi_s3.h to include/acpi/Simon Glass1-3/+1
This header relates to ACPI and we are about to add some more ACPI headers. Move this one into a new directory so they are together. The header inclusion in pci_rom.c is not specific to x86 anymore, so drop the #ifdef CONFIG_X86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-16pci: Adjust dm_pci_read_bar32() to return errors correctlySimon Glass1-1/+8
At present if reading a BAR returns 0xffffffff then the value is masked and a different value is returned. This makes it harder to detect the problem when debugging. Update the function to avoid masking in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-04-16dm: pci: Allow disabling auto-config for a deviceSimon Glass1-0/+2
Add a means to avoid configuring a device when needed. Add an explanation of why this is useful to the binding file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-30pci-host-ecam-generic: access config space independent of system-wide bus idVladimir Oltean1-4/+33
The pci-host-ecam-generic code assumes that the ECAM is the first PCI bus in the system to be probed. Therefore, the system-wide bus number allocated by U-Boot in sequence for it is going to be zero, which corresponds to the memory-mapped config spaces found within it. Reuse the logic from other PCI bus drivers, and assume that U-Boot will allocate bus numbers in sequence for all buses within the current ECAM. So the base number of the bus needs to be subtracted when indexing the correct config space. Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host controller") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-02-06dm: core: Create a new header file for 'compat' featuresSimon Glass8-0/+8
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-06dm: core: Require users of devres to include the headerSimon Glass2-0/+2
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-06dm: pci: Update a few more interfaces for const udevice *Simon Glass1-9/+9
Tidy up a few places where const * should be used. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-06dm: pci: Update the PCI read_config() method to const dev *Simon Glass22-43/+46
At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24pci: layerscape: device tree fixup based on SoC andWasim Khan3-0/+75
lx2160a rev1 requires layerscape_gen4 device tree fixup and lx2160a rev2 requires layerscape device tree fixup. Add device tree fixup for lx2160a based on SoC and Version. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24pci: layerscape: Move streamId allocation to common device tree fixupWasim Khan4-26/+31
Move streamId allocation to layerscape common device tree fixup. Calculate streamId based on SoC variant. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24pci: layerscape: Common device tree fixup for NXP SoCsWasim Khan5-8/+58
Add Common device tree fixup for NXP SoCs. Based on SoC and revision call pcie_layerscape or pcie_layerscape_gen4 fixup. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24pci: layerscape: Fix the BARs disable functionHou Zhiqiang1-11/+0
There is not any difference for disabling BARs in RC mode between PCIe controllers with and without SRIOV. Fixes: 80afc63fc342 ("pci: layerscape: add pci driver based on DM") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24pci: layerscape: Fix the disabling of Expansion ROM BARHou Zhiqiang1-1/+1
The software will still get non-zero Expansion ROM BAR size even when the BAR_EN bit is cleared. The BAR_EN bit of register EXP_ROM_BAR_MASK_RC is not working as expected, so this patch changes to mask all the bits. Fixes: 80afc63fc342 ("pci: layerscape: add pci driver based on DM") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-17common: Move ll_boot_init() to init.hSimon Glass1-0/+1
This is an init-related function so belongs in that file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-08pci: Print a warning if the bus is accessed before probingSimon Glass1-0/+13
It is not possible to access a device on a PCI bus that has not yet been probed, since the bus number is not known. Add a warning to catch this error. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07Merge tag 'u-boot-imx-20200107' of ↵Tom Rini1-0/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-imx New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
2020-01-07pci: imx: Add iMX6SX compatibleMarek Vasut1-0/+1
The driver works fine with iMX6SX, add the missing compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-01-02pci: layerscape: Manage PCIe EP compatible string via KconfigPankaj Bansal3-2/+11
The ep node device tree name is governed by these bindings: https://github.com/torvalds/linux/blob/master/Documentation/ devicetree/bindings/pci/layerscape-pci.txt#L24 As per above the ep compatible node contains platform name. Therefore, define the ep node compatible as CONFIG to find the pcie ep node in device tree during device tree fixup. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02pci: layerscape: move PCIE related CONFIG to PCI KconfigPankaj Bansal1-0/+15
move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26armv8: lx2160a: Add FSL_PEX_STREAM_ID_END for LX2160AWasim Khan1-1/+1
Add FSL_PEX_STREAM_ID_END and remove FSL_PEX_STREAM_ID_NUM for lx2160a. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26pci: layerscape_gen4: Suffix API names with _ls_gen4Wasim Khan1-8/+12
Update API names for layerscape gen4 fixup. Suffix layerscape_gen4 fixup API names with _ls_gen4. This is required to organize device tree fixup in common, layerscape and layerscape_gen4 specific code. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-07 13:44:34 +0300