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path: root/drivers/pci
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2023-08-12pci: rockchip: Release resources on failing probeJonas Karlman1-51/+57
The PCIe driver for RK3399 is affected by a similar issue that was fixed for RK35xx in the commit e04b67a7f4c1 ("pci: pcie_dw_rockchip: release resources on failing probe"). Resources are not released on failing probe, e.g. regulators may be left enabled and the ep-gpio may be left in a requested state. Change to use regulator_set_enable_if_allowed and disable regulators after failure to keep regulator enable count balanced, ep-gpio is also released on regulator failure. Also add support for the vpcie12v-supply, remove unused include and check return value from dev_read_addr_name. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-10pci: plda: Get correct ECAM offset in multiple PCIe RC caseMinda Chen1-2/+3
Get the correct ECAM offset and record the secondary bus number in Multiple RC case. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02starfive: pci: Add StarFive JH7110 pcie driverMason Huo5-0/+566
Add pcie driver for StarFive JH7110, Also add PLDA PCIe controller common driver functions. Several devices are tested: a) M.2 NVMe SSD b) Realtek 8169 Ethernet adapter. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-30spl: CONFIG_SPL_PCI_PNP should depend on CONFIG_SPL_PCIHeinrich Schuchardt1-1/+2
CONFIG_SPL_PCI_PNP=y without CONFIG_SPL_PCI=y makes no sense. Fixes: 32f5e9e5c1a7 ("nvme: pci: Enable for SPL") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-07-28pci: pcie_dw_rockchip: Disable unused BARs of the root complexJon Lin1-0/+8
The Root Complex BARs default to claim the full 1 GiB memory region on RK3568, leaving no space for any attached device. Fix this by disable the unused BAR 0 and BAR 1 of the RC. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [jonas@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28pci: pcie_dw_rockchip: Speed up link probeJonas Karlman1-31/+37
Use a similar pattern and delay values as the linux mainline driver to speed up failing when nothing is connected. Reduce fail speed from around 5+ seconds down to around one second on a Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowedJonas Karlman1-10/+7
The vpcie3v3 regulator is typically a fixed regulator controlled using gpio. Change to use enable and disable calls on the regulator instead of trying to set a voltage value. Also remove the delay to match linux driver, for a fixed regulator the startup-delay-us prop can be used in case a startup delay is needed. Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that this delay was not needed. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28pci: pcie_dw_rockchip: Get config region from reg propJonas Karlman2-4/+13
Get the config region to use from the reg prop. Also update the referenced region index used in comment. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-17pci: Mask the ROM address in case it is already enabledSimon Glass1-0/+1
In some cases the video ROM may have been enabled previously, such as by a previous firmware stage. Use the correct address in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17pci: Adjust video BIOS debugging to be SPL-friendlySimon Glass1-2/+2
A hex value is expected for the VGA mode. Add a 0x prefix, since the # construct is not supported in SPL. We don't want to add it, due to code-size constraints. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17x86: Pass video settings from SPL to U-Boot properSimon Glass1-21/+57
When video is set up in SPL, U-Boot proper needs to use the correct parameters so it can write to the display. Put these in a bloblist so they are available to U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17x86: Allow video-BIOS code to be built for SPLSimon Glass1-14/+14
With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e. SPL. Add a Kconfig option for this, adjust the Makefile rules and use CONFIG_IS_ENABLED() where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17pci: Tidy up logging and reporting for video BIOSSimon Glass1-3/+9
When running the ROM the code is not very helpful when something goes wrong. Add a little more debugging and some logging of return values to improve this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17pci: Support autoconfig in SPLSimon Glass2-1/+14
Allow PCI autoconfig to be handled in SPL, so that we can set it up correctly for boards which need to do this before U-Boot proper. This includes qemu-x64_64 which needs to set up the video device while in 32-bit mode. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-06-20nvme: pci: Enable for SPLMayuresh Chitale1-0/+6
Enable NVME and PCI NVMe drivers for SPL builds. Also enable PCI_PNP for SPL which is required to auto configure the PCIe devices. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
2023-06-12PCI: zynqmp: Add ZynqMP NWL PCIe root port driverStefan Roese3-0/+360
This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP NWL PCIe Bridge as root port. The driver source is partly copied from the Linux PCI driver and modified to enable usage in U-Boot (e.g. simplified and interrupt support removed). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Pali Rohár <pali@kernel.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20230525094918.111949-1-sr@denx.de Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-30pci: apple: Add support for M2 Pro/MaxMark Kettenis1-29/+71
The PCIe controller on the M2 Pro/Max is different from the one found on earlier Apple SoCs. Some registers moved and te meaning of the bits in some other registers changed. But they are still similar enough to handle both controllers in the same driver. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-05-17pci: pcie_dw_rockchip: Support max_link_speed dts propertyJon Lin1-1/+5
Add support for max_link_speed specified in the PCI DT binding. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [eugen.hristev@collabora.com: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> [jonas@kwiboo.se: switch to dev_read_u32_default] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17pci: pcie_dw_rockchip: Add rk3588 compatibleJon Lin1-0/+1
Add compatible for RK3588 SoC. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-11pci: coreboot: Don't read regions when bootingSimon Glass1-0/+4
When U-Boot is the second-stage bootloader, PCI is already set up. We cannot read the regions from the device tree. There is no point anyway, since PCI devices have already been allocated according to the regions and it is not safe for U-Boot to make any changes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Fixes: f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()") Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-09pci: pcie_dw_rockchip: release resources on failing probeEugen Hristev1-11/+30
Implement a resource release mechanism on failing probe. Without this, a strange situation can happen e.g. when init port fails, or attempting to get the PHY fails, because the gpios have been requested first, and if the user tries to do 'pci enum' again, the driver will fail with 'can't find reset gpios' even if the gpios are there, just because they were blocked by a previous probe attempt. It is only natural to release the acquired resources if the probe fails, just for consistency if nothing else. This way on subsequent probe attempts, the user will get the same error message, and not something different that doesn't make sense. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06drivers: use devfdt_get_addr_index_ptr when cast to pointerJohan Jonker3-8/+8
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use devfdt_get_addr_size_index_ptr when cast to pointerJohan Jonker1-3/+3
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use dev_read_addr_ptr when cast to pointerJohan Jonker1-2/+2
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use dev_read_addr_index_ptr when cast to pointerJohan Jonker2-8/+8
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_index_ptr instead of the dev_read_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-05pci: layerscape: add support for kernel/official fsl, ls1088a-pcie bindingMathew McBride1-0/+1
This allows the Layerscape PCIe RC driver to use the upstream style binding (two "reg" entries instead of four). It is similar to the previous commit e10da1f985ad ("pci: layerscape: add official ls1028a binding support") which implemented this for the LS1028A. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
2023-05-04pci: fsl: Do not access PCI BAR0 register of PCIe Root PortPali Rohár1-0/+14
Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0. PCIe Root Port does not have any PCIe memory, so returns zero when trying to read from PCIe Root Port BAR0 and ignore any writes. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-05-02pci: auto: Remove PCI_CLASS_PROCESSOR_POWERPC autoconfig casePali Rohár1-4/+0
PCI autoconfig case for PCI_CLASS_PROCESSOR_POWERPC just prints debug message and then calls autoconfig setup code like for any other standard endpoint device. We do not need special debug message for it, so remove this case and handle PCI_CLASS_PROCESSOR_POWERPC via default code path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-05-02pci: mpc85xx: Do not access PCI BARs registers of BDF address 00:00.0Pali Rohár1-0/+12
At BDF address 00:00.0 is fictional device which PCI configuration header is for configuring mpc85xx PCI controller itself. PCI config space of this device has ATMU inbound registers on position of PCI BARs. Trying to do PCI auto configuration of this device cause rewriting ATMU inbound registers. To avoid it, do not allow overwriting registers at BARs positions. And because this device does not have any PCI memory, return zeros when trying to read PCI BARs config space registers. It signals to auto configuration tool to not allocate any PCI memory for this device. This information is taken from MPC8544E Reference Manual, sections 17.3.1.3, 17.3.1.1.1, 17.3.2 and 17.3.2.11. Available at NXP website: https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
2023-05-02pci: mpc85xx: Do not try to access extended PCIe registersPali Rohár1-2/+10
Driver pci_mpc85xx.c is PCI controller driver for old PCI Local Bus, which does not support access to extended PCIe registers (above 0xff), as opposite of the PCIe driver pcie_fsl.c for the same platform. So do not try to access extended PCIe registers as it cannot work. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
2023-05-02pci: mpc85xx: Allow 8/16-bit access to PCI config spacePali Rohár1-2/+24
This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read and write access to PCI config space as described in more Freescale reference manuals. This change fixes issue that 8-bit and 16-bit write to PCI config space caused to clear adjacent bits of 32-bit PCI register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
2023-05-02pci: mpc85xx: Add missing sync() after writing to PCI config spacePali Rohár1-0/+1
On PowerPC we should use barrier after store operation to HW register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
2023-03-29pci: apple: Initialize only enabled portsJanne Grunau1-0/+2
The Linux devicetrees for Apple silicon devices are after review feedback switching from deleting unused PCIe ports to disabling them. Link: https://lore.kernel.org/asahi/1ea2107a-bb86-8c22-0bbc-82c453ab08ce@linaro.org/ Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2023-03-13efi: Support a 64-bit frame buffer addressSimon Glass1-4/+6
The current vesa structure only provides a 32-bit value for the frame buffer. Many modern machines use an address outside the range. It is still useful to have this common struct, but add a separate frame-buffer address as well. Add a comment for vesa_setup_video_priv() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07sh4: Drop unused pci_sh7780 driverSimon Glass2-93/+0
This is not used. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-27pci: Add Apple PCIe controller driverMark Kettenis3-0/+364
This driver supports the PCIe controller on the Apple M1 and M2 SoCs. The code is adapted from the Linux driver. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2022-12-23pci-rcar-gen3: Rename CONFIG_SEND_ENABLETom Rini1-3/+3
We rename the symbol CONFIG_SEND_ENABLE to just SEND_ENABLE, and remove the second whitespace following the define. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23global: Migrate CONFIG_PCIE_IMX_POWER_GPIO to CFGTom Rini1-5/+5
Perform a simple rename of CONFIG_PCIE_IMX_POWER_GPIO to CFG_PCIE_IMX_POWER_GPIO Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23global: Migrate CONFIG_PCIE_IMX_PERST_GPIO to CFGTom Rini1-6/+6
Perform a simple rename of CONFIG_PCIE_IMX_PERST_GPIO to CFG_PCIE_IMX_PERST_GPIO Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-12drivers: pci: pcie_dw_common: add upper-limit to iATUBen Dooks2-0/+3
The 4.6 spec added an upper 32bits to the ATU limit, and since this driver is already assuming the unrolled feature added in the 4.8 specification this really should be set. This is causing a bug with testing against the QEMU model as it defaults the viewports to fully open and not setting this causes the config viewport to become most of memory (obviously stopping the emulated system working correctly) Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
2022-12-06global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini5-10/+10
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-06global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*Tom Rini7-36/+36
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini1-1/+1
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-31Merge tag 'video-20221030' of ↵Tom Rini2-3/+1
https://source.denx.de/u-boot/custodians/u-boot-video - fix [hv]sync active vs back porch in dw_mipi_dsi - simplefb rotation support - support splash as raw image from MMC - enhancements to Truetype console (multiple fonts and sizes) - drop old LCD support
2022-10-30video: Rename CONFIG_DM_VIDEO to CONFIG_VIDEOSimon Glass1-1/+1
Now that all the old code is gone, rename this option. Driver model migration is now complete. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30pci: Drop test for DM_VIDEOSimon Glass1-2/+0
This is not needed anymore, since there is no other option. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-29dm: treewide: Do not use the return value of simple uclass iteratorMichal Suchanek1-12/+3
uclass_first_device/uclass_next_device return value will be removed, don't use it. With the current implementation dev is equivalent to !ret. It is redundant to check both, ret check can be replaced with dev check, and ret check inside the iteration is dead code. Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-29dm: core: Switch uclass_*_device_err to use uclass_*_device_checkMichal Suchanek1-4/+3
Clarify documentation, fix a few more cases that could be broken by the change. Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2022-10-18dm: pci: Fix device PCI iterationMichal Suchanek1-2/+2
When there is no PCI bus uclass_first_device will return no bus and no error which will result in pci_find_first_device calling skip_to_next_device with no bus, and the bus is only checked at the end of the while cycle, not the beginning. Fixes: 76c3fbcd3d ("dm: pci: Add a way to iterate through all PCI devices") Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-29dm: core: Drop ofnode_is_available()Simon Glass4-5/+5
This function is also available as ofnode_is_enabled(), so use that instead. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-07 15:19:14 +0300