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path: root/drivers/pci
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2019-12-03common: Move pci_init_board() out of common.hSimon Glass2-0/+2
This function can be dropped when all boards use driver model for PCI. For now, move it into init.h with a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-11Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini1-1/+5
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC. - Few bug fixes and updates related to SPI, hwconfig, ethernet, fsl-layerscape, pci, icid, PSCI
2019-11-08pci: layerscape: Only set EP CFG READY bitPankaj Bansal1-1/+5
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit of pci controller is set, so that RC can read the config space of EP. While setting the config ready bit, LTSSM_EN bit in same register was also inadvertently getting cleared. This restarts the link training between RC and EP. Update code to just set the desired CFG_READY bit (bit 0), while leaving the other bits unchanged. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08arm: add initial support for the Phytium Durian Boardliu hao3-0/+208
This adds platform code and the device tree for the Phytium Durian Board. The initial support comprises the UART and the PCIE. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-11-06pci: add DM based mpc85xx driverHeiko Schocher3-0/+166
add DM based PCI Configuration space access support for MPC85xx PCI Bridge. This driver is based on arch/powerpc/cpu/mpc85xx/pci.c In the old driver there is a fix for a hw issue on the TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I have no such hardware I did not port this part. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-10-12Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini1-6/+24
- Remember the device being emulated for Sandbox PCI - Update Kconfig options for FSP 1.0 - Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
2019-10-11pci: mediatek: add PCIe controller support for MT7623Ryder Lee3-0/+288
This adds PCIe controller support for MT7623. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11sandbox: pci: Remember the device being emulatedSimon Glass1-6/+24
Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08sandbox: pci: Create a new sandbox_pci_read_bar() functionSimon Glass1-0/+20
The code in swapcase can be used by other sandbox drivers. Move it into a common place to allow this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove inclusion of <asm/test.h> in pci_sandbox.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: pci: Drop the first parameter in pci_x86_r/w_config()Simon Glass1-2/+14
This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move acpi_s3.h to a common locationSimon Glass1-1/+1
At present this hedaer is only available on x86. To allow sandbox to use it for testing, move it to a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08pci: Show a message if PCI autoconfig failsSimon Glass1-3/+9
At present this fails silently which can be confusing since some devices on the PCI bus may not work correctly. Show a message in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add a '\n' in the PCI autoconfig fail message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08pci: Add more debug detail when resources are exhaustedSimon Glass1-1/+3
If PCI auto-config runs out of memory, show a few more details to help diagnose the problem. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: change %x to %llx to avoid build warnings on some platforms] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08pci: Disable autoconfig in SPLSimon Glass1-1/+1
At present U-Boot runs autoconfig in SPL but this is best left to U-Boot proper. For TPL and SPL we can normally used fixed BARs and save code size and time. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08pci: Show the result of binding a deviceSimon Glass1-1/+2
Update the debugging info a little to show the result of trying to bind a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08pci: sandbox: Probe PCI emulation devices when usedSimon Glass1-3/+2
At present PCI emulation devices are not probed before use, since they used to be children of the device that used them, and children cannot be probed before their parents. Now that PCI emulation devices are attached to the root node, we can simply probe them, and avoid using the internal function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08pci: sandbox: Move the emulators into their own nodeSimon Glass1-6/+30
Sandbox pci works using emulation drivers which are currently children of the pci device: pci-controller { pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; emul@1f,0 { compatible = "sandbox,swap-case"; }; }; }; In this case the emulation device is attached to pci device on address f800 (device 1f, function 0) and provides the swap-case functionality. However this is not ideal, since every device on a PCI bus has a child device. This is only really the case for sandbox, but we want to avoid special-case code for sandbox. Worse, child devices cannot be probed before their parents. This forces us to use 'find' rather than 'get' to obtain the emulator device. In fact the emulator devices are never probed. There is code in sandbox_pci_emul_post_probe() which tries to track when emulators are active, but at present this does not work. A better approach seems to be to add a separate node elsewhere in the device tree, an 'emulation parent'. This could be given a bogus address (such as -1) to hide the emulators away from the 'pci' command, but it seems better to keep it at the root node to avoid such hacks. Then we can use a phandle to point from the device to the correct emulator, and only on sandbox. The code to find an emulator does not interfere with normal pci operation. Add a new UCLASS_PCI_EMUL_PARENT uclass which allows finding an emulator given a bus, and finding a bus given an emulator. Update the existing device trees and the code for finding an emulator. This brings PCI emulators more into line with I2C. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix 3 typos in the commit message; encode bus number in the labels of swap_case_emul nodes; mention commit 4345998ae9df in sandbox_pci_get_emul()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: fsp: Create a common fsp_support.h headerSimon Glass1-1/+1
Many support functions are common between FSP1 and FSP2. Add a new header to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove forward declarations in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename existing FSP code to fsp1Simon Glass1-1/+1
Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-02pci: sh7751: Convert to DM and DT probingMarek Vasut1-58/+106
Convert the SH7751 PCI driver to DM and add DT probing. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2019-08-28dm: pcie_fsl: Add MPC8548 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for MPC8548 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P5040 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P5040 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P4080 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P4080 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P3041 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P3041 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P2041 PCIe supportHou Zhiqiang1-0/+7
Add compatible string for P2041 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCsHou Zhiqiang1-0/+7
Add compatible string for PCIe of P1020, P1021, P1024, P1025 and P2020 SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T104x PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T104x PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T102x PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T102x PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T4240 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T4240 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Fix the calculation of controller indexHou Zhiqiang2-2/+19
The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Fix the Class Code fixup functionHou Zhiqiang2-4/+16
The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdefHou Zhiqiang1-33/+36
This can avoid build error: The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only defined on the platforms that select the CONFIG_FOO, while it's not defined on platforms that do not select the CONFIG_FOO. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-13Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-4/+4
- Various improvements to Keymile boards - mostly DT conversation (Pascal & Holger) - Removal of now unsupported Keymile boards (Pascal & Holger) - Small MVEBU PCI fix (Marek) - Turris Omnia defconfig update (Marek) - Misc Allied Telesis defconfig updates (Chris)
2019-08-13Merge branch '2019-08-11-ti-imports'Tom Rini3-0/+732
- More DaVinci updates and fixes - PCIe support on am65x - Watchdog converted to DM - Assorted other bugfixes
2019-08-12pcie: ti: add driver for AM65x PCIe RCSekhar Nori3-0/+732
Add driver supporting PCIe root-complex available on TI's AM65x SoC. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12pci: pci_mvebu: set BAR0 after memory space is setMarek Behún1-4/+4
The non-DM version of this driver used to set BAR0 register after the calls to pci_set_region. I found out that for some strange reason the ath10k driver in kernel fails to work if this is done the other way around. I know that Linux's driver should not depend on how U-Boot does things, but for some strange reason it does and this seems to be the simplest solution. Fix it since it caused regressions on Omnia. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: VlaoMao <vlaomao@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-11env: Move env_get() to env.hSimon Glass3-0/+3
Move env_get() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11pci: intel: Fix configuration type based on secondary numberLey Foon Tan1-4/+6
This fix issue when access config from PCIe switch. The PCIe controller need to send Type 0 config TLP if the targeting bus matches with the secondary bus number, which is when the TLP is targeting the immediate device on the link. The PCIe controller send Type 1 config TLP if the targeting bus is larger than the secondary bus, which is when the TLP is targeting the device not immediate on the link. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11pci: intel: Fix error when enumerating multi-function PCIe deviceLey Foon Tan1-2/+4
Hardware return completion status non-zero when read from non exist function in multi-function PCIe device. Return error will cause PCIe enumeration fail. Change it to return 0 and return value 0xffffffff when error. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11pci: intel: Increase TLP polling counterLey Foon Tan1-1/+1
Some PCIe devices require longer time to response. Increase polling counter to 20000 (~100ms). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-07-13pci: ensure enumeration of all devices in pci_initMarek Behún1-2/+2
Use the uclass_first_device_check and uclass_next_device_check functions instead of uclass_first_device and uclass_next_device in pci_init. This ensures that all PCI devices are tried to be probed. Currently if a device fails to probe, the enumeration stops and the devices which come after the failed device are not probed. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: VlaoMao <vlaomao@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-11drivers: pci: add API to issue FLR on a PCI function if supportedAlex Marginean1-0/+24
Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function, if FLR is supported. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-11drivers: pci: add map_bar support for Enhanced AllocationAlex Marginean1-0/+46
Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-21pci: Avoid assigning PCI resources that are below 0x1000Bin Meng1-2/+3
commit b7598a43f2b4 ("[PATCH] Avoid assigning PCI resources from zero address") only moved the bus lower address to 0x1000 if the given bus start address is zero. The comment said 0x1000 is a reasonable starting value, hence we'd better apply the same adjustment when the given bus start address is below 0x1000. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2019-06-20dm: pci: add Freescale PowerPC PCIe driverHou Zhiqiang5-0/+725
Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-11pci: imx: Add DM and DT supportMarek Vasut1-6/+105
Add DM support and support for probing the iMX PCI driver from DT. The legacy non-DM support is retained, however shall be removed once DM PCI is the only option remaining. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11pci: imx: Pass driver private data aroundMarek Vasut1-19/+25
Pass the driver private data around the driver as much as possible, instead of having it as a static global variable. This is done in preparation for the DM conversion, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11pci: imx: Fix potential 64bit memory access clampingMarek Vasut1-9/+11
The driver limits the config space base to 32bit, however it can be 64bit on 64bit iMX hardware too. Remove that limitation. This patch has no impact on the iMX6, which is the only SoC currently supported by this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-11pci: imx: Factor out hard-coded register base addressesMarek Vasut1-31/+44
Pull out hard-coded register base addresses into driver private structure in preparation for DM conversion. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-27Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini3-0/+420
- Gen3 PCIe driver + enablement on Salvator-X platforms. - Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon. - SDHI HS400 fixes ported from latest BSP and datasheet.
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-17 00:02:51 +0300