|
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.
+----------------+
| | +------+
| USB3 OTG CTRL0 |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY0 |
+----------------+ | | | |
| | | | +------------+
| SATA CTRL0 |---->| |
| | +------+
+----------------+
+----------------+
| | +------+
| USB3 HOST CTRL1|---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY1 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL1 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | | +------+
| QSGMII CTRL |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY2 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL2 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | |
| PCIe2 1-Lane |---
| |
+----------------+
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
