starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Collapse)	Author	Files	Lines
2023-05-17	phy: rockchip: naneng-combphy: Support rk3588	Jon Lin	1	-0/+95
	Add support for rk3588 phy variant. The PHY clock is fixed at 100MHz. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [kever.yang@rock-chips.com: update pcie pll parameters] Co-developed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [eugen.hristev@collabora.com: squashed, tidy up] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17	phy: rockchip: naneng-combphy: Add support for multiple resets	Eugen Hristev	1	-4/+4
	Some variants of the PHY have more than just one reset. To cover all cases, request the rests in bulk rather than just the reset at index 0. Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28	drivers: phy: add naneng combphy for rk3568	Jagan Teki	1	-0/+441
	RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers share one pipe interface for each combo phy, here is the diagram of the complex connection. +----------------+ \| \| +------+ \| USB3 OTG CTRL0 \|---->\| \| \| \| \| \| +------------+ +----------------+ \| PIPE \| \| \| \| MUX \|---->\| Combo PHY0 \| +----------------+ \| \| \| \| \| \| \| \| +------------+ \| SATA CTRL0 \|---->\| \| \| \| +------+ +----------------+ +----------------+ \| \| +------+ \| USB3 HOST CTRL1\|---->\| \| \| \| \| \| +------------+ +----------------+ \| PIPE \| \| \| \| MUX \|---->\| Combo PHY1 \| +----------------+ \| \| \| \| \| \|---->\| \| +------------+ \| SATA CTRL1 \| -->\| \| \| \| \| +------+ +----------------+ \| \| +----------------+ \| \| \| \| +------+ \| QSGMII CTRL \|---->\| \| \| \| \| \| +------------+ +----------------+ \| PIPE \| \| \| \| MUX \|---->\| Combo PHY2 \| +----------------+ \| \| \| \| \| \|---->\| \| +------------+ \| SATA CTRL2 \| -->\| \| \| \| \| +------+ +----------------+ \| \| +----------------+ \| \| \| \| \| PCIe2 1-Lane \|--- \| \| +----------------+ Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>