summaryrefslogtreecommitdiff
path: root/drivers/phy
AgeCommit message (Collapse)AuthorFilesLines
2021-07-29Merge tag 'ti-v2021.10-rc2' of ↵Tom Rini9-0/+4398
https://source.denx.de/u-boot/custodians/u-boot-ti - Add MMC High speed modes for AM64 and J7200 - Add Sierra/Torrent SERDES driver - Minor clean-ups for R5F boot from SPL
2021-07-28Makefile: Move phy rules into drivers/phySimon Glass1-0/+5
These don't belong in the drivers Makefile so move them down into the correct place. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup some missing dependencies this exposed] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-27phy: meson-axg-mipi: Access parent ofnode through dev_ofnode()Alper Nebi Yasak1-1/+1
With commit 84a42ae36683 ("dm: core: Rename device node to indicate it is private") and commit f10643cf8a4c ("dm: core: Access device ofnode through functions") accesses to the "node" member were replaced with dev_ofnode(). Also apply that replacement here. Fixes: 4547551aa019 ("phy: Add Amlogic AXG MIPI PCIe Analog PHY driver") Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-07-27phy: meson-axg-mipi: Rename "priv_auto_alloc_size" to "priv_auto"Alper Nebi Yasak2-2/+2
With commit 41575d8e4c33 ("dm: treewide: Rename auto_alloc_size members to be shorter") "priv_auto_alloc_size" was renamed to "priv_auto". Apply the rename to these two drivers as well. Fixes: 4547551aa019 ("phy: Add Amlogic AXG MIPI PCIe Analog PHY driver") Fixes: 7ef19503bacf ("phy: Add Amlogic AXG MIPI D-PHY driver") Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-07-27phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCJean-Jacques Hiblot5-0/+1168
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
2021-07-27phy: cadence: Add driver for Torrent SERDESAswath Govindraju3-0/+2470
Add driver for Torrent SERDES. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-9-kishon@ti.com
2021-07-27phy: cadence: Add driver for Sierra PHYAlan Douglas5-0/+760
Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵Tom Rini3-0/+205
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQYe Li3-0/+205
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-14phy: Add driver for ST-Ericsson AB8500 USB PHYStephan Gerhold3-0/+59
The AB8500 PMIC contains an USB PHY that needs to be set up in device or host mode to make USB work properly. Add a simple driver for the generic PHY uclass that allows enabling it. The if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) might be a bit strange. The USB PHY must be configured in either host or device mode and somehow the USB PHY driver must be made aware of the mode. Actually, the MUSB driver used together with this PHY does not support dynamic selection of host/device mode in U-Boot at the moment. Therefore, one very simple approach that works fine is to select the mode to configure at compile time. When the MUSB driver is configured in host mode the PHY is configured in host mode, and similarly when the MUSB driver is configured in device/gadget mode. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-14phy: socionext: Add UniPhier PCIe PHY driverKunihiko Hayashi3-0/+77
Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-10phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSBPaul Kocialkowski1-1/+13
Recent Allwinner platforms (starting with the H3) only use the MUSB controller for peripheral mode and use HCI for host mode. As a result, extra steps need to be taken to properly route USB signals to one or the other. More precisely, the following is required: * Routing the pins to either HCI/MUSB (controlled by PHY); * Enabling USB PHY passby in HCI mode (controlled by PMU). The current code will enable passby for each PHY and reroute PHY0 to MUSB, which is inconsistent and results in broken USB peripheral support. Passby on PHY0 must only be enabled when we want to use HCI. Since host/device mode detection is not available from the PHY code and because U-Boot does not support changing the mode dynamically anyway, we can just mux the controller to MUSB if it is enabled and mux it to HCI otherwise. This fixes USB peripheral support for platforms with PHY0 dual-route, especially H3/H5 and V3s. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-29phy: marvell: utmi: update utmi config which fixes usb2.0 instabilityGrzegorz Jaszczyk2-5/+27
- Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values. Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: add support for SFI1Igal Liberman2-7/+9
In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29phy: marvell: fix pll initialization for second utmi portGrzegorz Jaszczyk2-13/+32
According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: allow to initialize up to 6 USB portsGrzegorz Jaszczyk1-1/+1
New products can contain up to 6 usb ports, therefore allow to initialize all relevant UTMI PHYs. Change-Id: I28c36e59fa0e3e338bb3ee0cee2240b923f39785 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
2021-04-29phy: marvell: cp110: mark u-boot power-off callsIgal Liberman1-2/+2
It helps ATF to determine who called power off function (U-boot/Linux) and act accordingly Change-Id: Icfc5cbfdba64754496812154272b28c0ff639f0f Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: fix handling of unconnected comphyChristine Gharzuzi1-0/+4
- the default value of comphy pipe selector is set to PCIe (x4) in case of unconnected comphy the default value remains 0x4 which may lead to several issues with comphy initialization. - this patch adds SMC call that powers off the comphy lane in case of unconnected comphy. Change-Id: I196b2916518dd8df3b159ffa85e2989b8e483087 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: pass sgmii id to firmwareIgal Liberman1-22/+5
Currently, we don't pass id for SGMII 0/1. A bug in comphy selector configuration was found (in comphy firmware), after fixing it, SGMII0/1 have different configuration, so we need to pass the ID the firmware. Change-Id: Idcff4029cc9cf018278e493221b64b33574e0d38 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: cp110: clean up driver after it was moved to atfGrzegorz Jaszczyk5-777/+0
Change-Id: I358792a96c13b54e700c05227cc7a8f6bd584694 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: remove both phy and pipe selector configurationGrzegorz Jaszczyk1-94/+0
Now the comphy configuration is handled in atf, therefore there is no need to configure phy or pipe selector in u-boot, it is configured by atf for each particular pair: lane and mode. Change-Id: I0bebf8d5ff66dbeb6bf9ef90876195938a8eb705 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: let the firmware perform training for XFIGrzegorz Jaszczyk1-179/+18
Replace the XFI training with appropriate SMC call, so the firmware will perform exact initialization. Update Stefan 2021-03-23: Move comphy_smc() function to an earlier place - necessary for the mainline merge. Change-Id: I789b130b05529dc80dadcf66aef407d93595b762 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: let the firmware configure comphy for USBGrzegorz Jaszczyk1-124/+9
Replace the comphy initialization for USB with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: I7f773c0dfac70db9dd2653de2cdcfac577e78c4e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: cp110: let the firmware configure comphy for RXAUIGrzegorz Jaszczyk1-180/+4
Replace the comphy initialization for RXAUI with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: Iedae0285fb283e05bb263a8b4ce46e8e7451a309 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: remove unused definitionsMarcin Wojtas2-11/+6
Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it. This patch removes unused definitions. Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29phy: marvell: enable comphy info prints for all devicesIgal Liberman1-2/+1
Change-Id: I3b97253e7102a0868440a9e0200acc1c7919c743 Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: add RX training commandIgal Liberman4-3/+281
This patch adds support for running RX training using new command called "rx_training" Usage: rx_training - rx_training <cp id> <comphy id> RX training allows to improve link quality (for SFI mode) by running training sequence between us and the link partner, this allows to reach better link quality then using static configuration. Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2021-04-29phy: marvell: save comphy_map_data priv structureIgal Liberman2-10/+11
This allows the lower level driver access to comphy map data (required for RX training support, which is introduced in the following patches). Change-Id: Ib7ffdc4b32076c01c3a5d33f59552c9dfc6b12fa Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: fix several minor bugs in comphy_probeIgal Liberman1-10/+19
If fdtdec_get_int can't find speed, set COMPHY_SPEED_INVALID If fdtdec_get_int can't find type, set COMPHY_TYPE_INVALID Move the error print if phy-type is invalid Add continue to the probe loop (in a case of invalid phy) Cosmetic changes Change-Id: I0c61b40bfe685437426fe907942ed338b7845378 Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: utmi: update analog parameters according to latest ETPIgal Liberman2-7/+7
Add UTMI analog parameters initialization values according to latest ETP. Change-Id: I5bcca205a3995202a18ff126f371a81f69e205c8 Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: cp110: initialize only enabled UTMI unitsOmri Itach1-25/+26
UTMI should be initialized only for enabled device tree nodes. This fix overrides current internal configuration array entry with the next DT entry data if error is detected during the current DT entry parsing or the current port is disabled. This way the internal configuration structure will only contain valid ports information obtained from the DT. Change-Id: I9c43c6a5d234e15ae9005d1c9bc983fc1f3544b8 Signed-off-by: Omri Itach <omrii@marvell.com> Signed-off-by: Ken Ma <make@marvell.com>
2021-04-29phy: marvell: add missing speed during info printsIgal Liberman1-2/+3
In get_speed_string() we have an array (speed_strings[]) which includes all possible speed strings. This array size and content must be aligned to the speed defines in comphy_data.h. This patch adds missing 5.125G speed, aligns speed_strings[] and fixes incorrect printing when speed > 5.0G. Change-Id: I9900d23595094be321be0c62fcaa88036324568e Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: rename comphy related definitions to COMPHY_XXIgal Liberman4-103/+115
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29phy: marvell: add comphy type PHY_TYPE_USB3jinghua1-1/+1
- For some Marvell SoCs, like armada-3700, there are both USB host and device controller, but on PHY level the configuration is the same. - The new type supports both USB device and USB host - This patch is cherry-picked from u-boot-2015 as-is. Change-Id: I01262027edd8ec23391cff6fb409b3009aedfbb9 Signed-off-by: jinghua <jinghua@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-19phy: meson-g12a-usb3-pcie: add support for PCIe opsNeil Armstrong1-4/+77
Add the PCIe part of the G12A USB3 PCIe Combo PHY driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-18phy: nop-phy: Add standard usb-nop-xceiv compat stringMarek Vasut1-0/+1
The USB no-op PHY uses "usb-nop-xceiv" compatible string. This driver is compatible with USB no-op PHY, so add the compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-02-15Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini9-0/+9
- Merge the patch to take <asm/global_data.h> out of <common.h>
2021-02-10phy: Add Amlogic AXG MIPI PCIe Analog PHY driverNeil Armstrong3-0/+243
The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time, and provides the Analog part of MIPI DSI transmission and Analog part of the PCIe lines. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10phy: Add Amlogic AXG MIPI D-PHY driverNeil Armstrong3-0/+403
The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. This D-PHY depends on a separate analog PHY. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10generic-phy: add configure opNeil Armstrong1-0/+11
Add the PHY configure op callback to the generic PHY uclass to permit configuring the PHY. It's useful for MIPI DSI PHYs to setup the link timings. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10phy: dphy: Add configuration helpersNeil Armstrong3-0/+167
The MIPI D-PHY spec defines default values and boundaries for most of the parameters it defines. Introduce helpers to help drivers get meaningful values based on their current parameters, and validate the boundaries of these parameters if needed. These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass9-0/+9
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-24phy: add USB PHY driver for MediaTek MT7620 SoCWeijie Gao3-0/+118
This patch adds USB PHY driver for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-21pci: Add Rockchip dwc based PCIe controller driverShawn Lin1-0/+3
Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHYShawn Lin3-0/+164
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as part of Generic PHY framework. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-13phy: stm32-usbphyc: migrate trace to dev and log macroPatrick Delaunay1-8/+10
Change pr_debug to log_debug or dev_dbg macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-06Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini1-1/+1
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
2021-01-06Merge tag 'v2021.01-rc5' into nextTom Rini1-1/+1
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05dm: core: Access device ofnode through functionsSimon Glass1-1/+1
At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-15 14:34:36 +0300