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path: root/drivers/ram
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2023-07-20board: starfive: evb: use dram_init in splSamin Guo1-2/+0
dram_init call fdtdec_setup_mem_size_base, so starfive_ddr.c do not need it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-19dram: starfive: jh7110: Add ddr4 supportSamin Guo6-68/+2706
Add ddr4 tuning support (sync from devkits) Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: starfive: jh7110: Add 1G supportSamin Guo4-29/+46
add 1G DDR tuning cfg Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-23board: starfive: copyright: Standardize the copyright formatYanhong Wang6-7/+6
Unify the content format of the copyright section Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2022-10-18ram: starfive: Make DDR driver support 8G sizeYan Hong Wang4-733/+547
This patch include four items: 1.rename the driver compatible name. 2.reset action with the common API. 3.clean up code to make it is closer to readable. 4.add configuration to support 8G size Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18ram: starfive: jh7110: Replace the configuration operation for pll1 clkYan Hong Wang2-27/+6
Replace the configuration operation for pll1 clk with common api provide by pll module. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: Make ddr driver support 2G sizeyanhong.wang4-25/+250
The ddr driver include two configs with 2G and 4G.Fist read the ddr size config from the memory node in the dts,then match the right config and do it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: add ddr driveryanhong.wang10-0/+3203
Add driver for JH7110 to support ddr initialization in SPL. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com> Signed-off-by: samin <samin.guo@starfivetech.com>
2021-08-02global: Convert simple_strtoul() with decimal to dectoul()Simon Glass1-1/+1
It is a pain to have to specify the value 10 in each call. Add a new dectoul() function and update the code to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-18rockchip: rk3568: Add sdram driverJoseph Chen2-0/+57
Add the driver for rk3568 u-boot to get sdram capacity. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-05-31drivers: ram: sifive: rename fu540_ddr and add fu740 supportGreen Wan3-49/+50
Rename fu540_ddr.c to sifive_ddr.c and add fu740 support Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-12ram: k3-ddrss: Enable vtt regulator if presentLokesh Vutla1-0/+14
Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce support for AM642 SoCsDave Gerlach20-0/+23490
Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce common driver with J7 SoC supportDave Gerlach27-3849/+3675
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSSDave Gerlach2-2/+11
Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: Rename to k3-ddrssDave Gerlach20-1/+1
Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation of introducing additional support for other platforms to the same driver. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for typesDave Gerlach1-1514/+1514
Use Linux style u32 instead of uint32_t. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_pi_macros: Fix indentation issuesDave Gerlach1-2801/+2801
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issuesDave Gerlach1-694/+694
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issuesDave Gerlach1-3681/+3681
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issuesDave Gerlach1-717/+717
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issuesDave Gerlach1-167/+167
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23mips: octeon: Misc changes required because of the newly added headersStefan Roese2-28/+22
With the newly added headers and their restructuring (which macro is defined where), some changes in the already existing Octeon files are necessary. This patch makes the necessary changes. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-09Merge tag 'u-boot-stm32-20210409' of ↵Tom Rini1-0/+3
https://source.denx.de/u-boot/custodians/u-boot-stm Add rt-thread art-pi board support based on STM32H750 SoC Add Engicam i.Core STM32MP1 SoM Add FIP header support for STM32programmer Update uart number when no serial device found for STM32MP1 Remove board_check_usb_power function when ADC flag is not set Update SPL size limitation for STM32MP1 Set soc_type, soc_pkg, soc_rev env variables for STM32MP1
2021-04-09ram: stm32: fix strsep failed on read only memorydillon min1-0/+3
strsep will change data from original memory address, in case the memory is in non-sdram/sram place, will run into a bug(hang at SDRAM: ) just add a temporary array to store bank_name[] to fix this bug. Signed-off-by: dillon min <dillon.minfei@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-04-08riscv: sifive: Rename fu540 board to unleashedBin Meng1-1/+1
In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass9-0/+9
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-18ram: aspeed: Add AST2600 DRAM control supportDylan Hung3-2/+1123
AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-17ram: k3-j721e: rename BIT_MASK()Heinrich Schuchardt2-15/+19
The macro BIT_MASK is already defined in include/linux/bitops.h. To avoid name collisions rename BIT_MASK() in drivers/ram/k3-j721e/lpddr4_private.h to LPDDR4_BIT_MASK(). Remove superfluous parantheses. Remove superfluous comparison to 0. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-13ram: stm32mp1: migrate trace to dev or log macroPatrick Delaunay5-104/+117
Define LOG_CATEGORY, use dev_ macro when it is possible and migrate other trace to log_ macro. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13ram: stm32: migrate trace to log macroPatrick Delaunay1-4/+6
Define LOG_CATEGORY, change debug to dev_dbg and remove "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-12-14dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass6-27/+22
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass10-20/+20
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass9-30/+30
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass10-10/+10
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass20-28/+28
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-31Merge tag 'u-boot-rockchip-20201031' of ↵Tom Rini2-0/+29
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
2020-10-30ram: rockchip: px30: add a config-based ddr selectionHeiko Stuebner2-0/+29
The SRAM on the PX30 is not big enough to hold multiple DDR configs so it needs to be selected during build. So far simply the DDR3 config was always selected and getting DDR4 or LPDDR2/3 initialized would require a code modification. So add Kconfig options similar to RK3399 to allow selecting the DDR4 and LPDDR2/3 options instead, while DDR3 stays the default as before. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-22common: rename getc() to getchar()Heinrich Schuchardt1-1/+1
The sandbox is built with the SDL2 library with invokes the X11 library which in turn calls getc(). But getc() in glibc is defined as int getc(FILE *) This does not match our definition. int getc(void) The sandbox crashes when called with parameter -l. Rename our library symbol getc() to getchar(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16ram: imxrt: Include device_compat.hSean Anderson1-0/+1
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-08ram: add ddr4 dual x8 configurationDylan Hung3-1/+12
the aspeed ddr sdram controller needs to know if the memory chip mounted on the board is dual x8 die or not. Or it may get the wrong size of the memory space. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-08ram: move aspeed ram driver into drivers/ directoryDylan Hung3-0/+443
to improve the maintainability. It is more easier to modify and add configurations of the driver in the centralized ram driver directory. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-07ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)Aaron Williams5-0/+435
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)Aaron Williams1-0/+11030
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 2 includes the very complex Octeon 3 DDR4 configuration Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)Aaron Williams1-0/+2728
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 1 adds the base U-Boot RAM driver, which will be instantiated by the DT based probing. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-09-30ram: sifive: Remove regmap dependencyBin Meng1-9/+3
The usage of regmap API in the SiFive RAM driver is not correct. The reg address should be obtained via dev_read_addr_index() API. Signed-off-by: Bin Meng <bin.meng@windriver.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-02 10:45:15 +0300