summaryrefslogtreecommitdiff
path: root/drivers/reset
AgeCommit message (Collapse)AuthorFilesLines
2019-08-11env: Move env_get() to env.hSimon Glass1-0/+1
Move env_get() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-07-21sysreset: add support for socfpga sysresetSimon Goldschmidt1-0/+19
This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga to a UCLASS_SYSRESET based dm driver. A side effect is that gen5 and a10 can now select between cold and warm reset. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-10reset: socfpga: convert to livetreeSimon Goldschmidt1-3/+1
Convert 'socfpga_reset_probe' to use 'dev_read_u32_default' instead of 'fdtdec_get_int'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-08Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini1-17/+36
- H6 Beelink GS1 board (Clément) - Olimex A64-Teres-I board (Jonas) - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) - Change include order (Jagan) - EPHY clock changes (Jagan) - EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
2019-05-08reset: Get the RESET by index without deviceJagan Teki1-17/+36
Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode. So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-01rockchip: use 'arch-rockchip' as header file pathKever Yang1-1/+1
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-04-24Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogicTom Rini1-0/+1
- Add support for Amlogic p200 & p201 Reference Designs - Add Amlogic SoC information display - Add support for the Libretech-AC AML-S805X-AC board - Add Amlogic AXG reset compatible - Add I2C support for Amlogic AXG - Fix AXG PIN and BANK pinctrl definitions - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset - Add initial support for Amlogic G12A SoC and U200 board - Enable PHY_REALTEK for selected boards - Fix Khadas VIM2 README
2019-04-24reset: add reset driver for HiSilicon platformShawn Guo3-0/+110
It adds a Driver Model compatible reset driver for HiSlicon platform. The driver implements a custom .of_xlate function, and uses .data field as reset register offset and .id field as bit shift. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-17reset: socfpga: add reset handling for old kernelsSimon Goldschmidt1-0/+44
This adds code to take peripherals out of reset based on an environment variable. This is in preparation for removing the code that does this from SPL. However, some drivers even in current Linux cannot handle peripheral reset, so until this works, we need a compatibility workaround. This workaround is implemented in the 'assert' and 'remove' callbacks of this reset driver: the 'assert' callback does not disable peripherals that were already taken out of reset, while the 'remove' callback, which is called on OS_PREPARE, deasserts all peripheral resets if the environment variable "socfpga_legacy_reset_compat" is set to 1, which is what the gen5 SPL did up to now. This is in preparation to clean up the SPL and implementing proper reset handling for U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17reset: socfpga: rename membase ptr to modrst_baseSimon Goldschmidt1-5/+6
The only member of this driver's priv struct is a pointer, which is called 'membase'. However, since this driver handles multiple sub- architectures, this is not the base address from dts but the base address of some common registers of those sub-arches. Reflect this better in sourcecode by renaming 'membase' to 'modrst_base'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-10reset-meson: Add AXG reset compatibleNeil Armstrong1-0/+1
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-01-18reset: Add Allwinner RESET driverJagan Teki3-0/+133
Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-15reset: MedaiTek: add reset controller driver for MediaTek SoCsWeijie Gao3-0/+110
This patch adds reset controller driver for MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay1-1/+2
Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-09-11reset: Introduce TI System Control Interface (TI SCI) reset driverAndreas Dannenberg3-0/+215
Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a reset driver that communicates to the system controller over the TI SCI protocol for performing reset management of various devices present on the SoC. Various reset functionalities are achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/reset/reset-ti-sci.c driver of the Linux kernel. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11dm: reset: Update uclass to allow querying reset statusAndreas Dannenberg1-0/+9
Add a reset operations function pointer to support querying the current status of a reset control. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-07-20misc: stm32: Add STM32MP1 supportPatrick Delaunay1-13/+3
Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-06-22reset: uniphier: sync reset data with Linux 4.18-rc1Masahiro Yamada1-5/+8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-01reset: bcm6345: convert to use live dtÁlvaro Fernández Rojas1-6/+2
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-05-07regmap: change regmap_init_mem() to take ofnode instead udeviceMasahiro Yamada1-1/+1
Currently, regmap_init_mem() takes a udevice. This requires the node has already been associated with a device. It prevents syscon/regmap from behaving like those in Linux. Change the first argumenet to take a device node. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-07regmap: clean up regmap allocationMasahiro Yamada1-1/+1
Putting zero length array at the end of struct is a common technique to embed arbitrary length of members. There is no good reason to let regmap_alloc_count() branch by "if (count <= 1)". As far as I understood the code, regmap->base is an alias of regmap->ranges[0].start, but it is not helpful but make the code just ugly. Rename regmap_alloc_count() to regmap_alloc() because the _count suffix seems pointless. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: fixup cpu_info-rcar.c] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini13-26/+13
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini2-4/+0
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-18Merge git://git.denx.de/u-boot-uniphierTom Rini1-0/+5
2018-04-18reset: uniphier: add ethernet reset control supportKunihiko Hayashi1-0/+5
Add reset lines for ethernet controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-18Merge git://git.denx.de/u-boot-socfpgaTom Rini3-0/+113
2018-04-18reset: fix reset_get_bulk when phandle errorNeil Armstrong1-2/+2
This fixes the Coverity Defect CID 175348 when dev_count_phandle_with_args() returns a negative value. Fixes: 0c28233903b5 ("reset: Add get/assert/deassert/release for bulk of reset signals") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-04-17reset: socfpga: add reset driver for SoCFPGA platformDinh Nguyen3-0/+113
Add a DM compatible reset driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-10reset: add sandbox test for bulk APINeil Armstrong2-1/+30
This patch adds the bulk reset API tests for the sandbox test suite. Unlike the main test, it also check the "other" reset signal using the bulk API and checks if the resets are correctly asserted/deasserted. To allow the bulk API to work, and avoid changing the DT, the number of resets of the sandbox reset controller has been bumped to 101 for the "other" reset line to be valid. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-10reset: Add get/assert/deassert/release for bulk of reset signalsNeil Armstrong1-0/+60
This patch adds a "bulk" API to the reset API in order to get/deassert/ assert/release a group of reset signals associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of reset signals in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-10reset: Add Amlogic Meson Reset ControllerNeil Armstrong3-0/+99
The Amlogic Meson SoCs embeds up to 256 reset lines, add the corresponding driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-19reset: stm32: adapt driver for stm32mp1Patrick Delaunay2-7/+31
- move to livetree and allow to get address to parent - add stm32mp1 compatible for probe Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas1-2/+2
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-09rockchip: reset: support a (common) rockchip reset driversElaine Zhang3-0/+143
Create driver to support the soft reset (i.e. peripheral) of all Rockchip SoCs. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); } reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl); i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c"; Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed commit tag:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-06stm32: fix STMicroelectronics copyrightPatrice Chotard1-2/+2
Uniformize STMicroelectronics copyrights headers for STM32 related code. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06sti: fix STMicroelectronics copyrightPatrice Chotard1-2/+2
Uniformize all STMicroelectronics copyrights headers for STi related code. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-15reset: uniphier: fix the first argument passed to dev_err()Masahiro Yamada1-1/+2
priv->dev does not exist. Pass the correct pointer to udevice. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada1-5/+5
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22dm: reset: add stm32 reset driverPatrice Chotard3-0/+88
This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-30reset: uniphier: add PXs3 supportMasahiro Yamada1-0/+23
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30reset: uniphier: fix compatible for SD reset node for LD11/LD20Masahiro Yamada1-1/+5
LD20 has SD ctrl instead of MIO ctrl. LD11 has both of them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20reset: uniphier: refactor reset data and add NAND/eMMC reset linesMasahiro Yamada1-46/+17
- Merge sys_reset data of LD4, Pro4, sLD8 and Pro5 - Merge sys_reset data of LD11 and LD20 - Use primitive UNIPHIER_RESETX() macro because bit assignments for system reset will be changed for every SoC in the future - Add NAND and eMMC resets Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20ARM: uniphier: remove sLD3 SoC supportMasahiro Yamada1-11/+3
This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-29reset: add reset_release_all()Patrice Chotard1-0/+25
Add reset_release_all() method which Assert/Free an array of resets signal that has been previously successfully requested by reset_get_by_*() Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-29reset: add reset_request()Patrice Chotard1-0/+9
This is needed in error path to assert previously deasserted reset by using a saved reset_ctl reference. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-25ARM: uniphier: fix various sparse warningsMasahiro Yamada1-9/+9
Fix warnings reported by sparse: - ... was not declared. Should it be static?" - cast to restricted __be32 While fixing those, the type conflict of cci500_init() was found. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-05reset: sti: add deassert counter in reset channel descriptorPatrice Chotard1-11/+30
This deassert counter allow to manage "shared" reset lines encountered in some specific case. On STiH410 SoC, DWC3, EHCI and OHCI are all using a respective PHY, but all of these PHYs shared a "global" reset. Currently, during command "usb stop", all host controller are stopped (XHCI, EHCI and OHCI). XHCI is first shutdowned, which means that PHY global reset is asserted. Then EHCI is shutdowned, but its PHY reset has already been asserted which make handshake() call failed in ehci_shutdown(). This counter allows to really assert a reset lines only when the "last" user is asserting it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: reset: Update uclass to support livetreeSimon Glass1-11/+10
Update the reset domain uclass to support livetree. Fix the xlate() method which has no callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass2-2/+2
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Use dm.h header when driver mode is usedSimon Glass1-1/+1
This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-30 00:03:36 +0300