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2017-11-06stm32: fix STMicroelectronics copyrightPatrice Chotard1-2/+2
Uniformize STMicroelectronics copyrights headers for STM32 related code. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-06sti: fix STMicroelectronics copyrightPatrice Chotard1-2/+2
Uniformize all STMicroelectronics copyrights headers for STi related code. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-15reset: uniphier: fix the first argument passed to dev_err()Masahiro Yamada1-1/+2
priv->dev does not exist. Pass the correct pointer to udevice. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada1-5/+5
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22dm: reset: add stm32 reset driverPatrice Chotard3-0/+88
This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-30reset: uniphier: add PXs3 supportMasahiro Yamada1-0/+23
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30reset: uniphier: fix compatible for SD reset node for LD11/LD20Masahiro Yamada1-1/+5
LD20 has SD ctrl instead of MIO ctrl. LD11 has both of them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20reset: uniphier: refactor reset data and add NAND/eMMC reset linesMasahiro Yamada1-46/+17
- Merge sys_reset data of LD4, Pro4, sLD8 and Pro5 - Merge sys_reset data of LD11 and LD20 - Use primitive UNIPHIER_RESETX() macro because bit assignments for system reset will be changed for every SoC in the future - Add NAND and eMMC resets Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-20ARM: uniphier: remove sLD3 SoC supportMasahiro Yamada1-11/+3
This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-29reset: add reset_release_all()Patrice Chotard1-0/+25
Add reset_release_all() method which Assert/Free an array of resets signal that has been previously successfully requested by reset_get_by_*() Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-29reset: add reset_request()Patrice Chotard1-0/+9
This is needed in error path to assert previously deasserted reset by using a saved reset_ctl reference. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-25ARM: uniphier: fix various sparse warningsMasahiro Yamada1-9/+9
Fix warnings reported by sparse: - ... was not declared. Should it be static?" - cast to restricted __be32 While fixing those, the type conflict of cci500_init() was found. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-05reset: sti: add deassert counter in reset channel descriptorPatrice Chotard1-11/+30
This deassert counter allow to manage "shared" reset lines encountered in some specific case. On STiH410 SoC, DWC3, EHCI and OHCI are all using a respective PHY, but all of these PHYs shared a "global" reset. Currently, during command "usb stop", all host controller are stopped (XHCI, EHCI and OHCI). XHCI is first shutdowned, which means that PHY global reset is asserted. Then EHCI is shutdowned, but its PHY reset has already been asserted which make handshake() call failed in ehci_shutdown(). This counter allows to really assert a reset lines only when the "last" user is asserting it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: reset: Update uclass to support livetreeSimon Glass1-11/+10
Update the reset domain uclass to support livetree. Fix the xlate() method which has no callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass2-2/+2
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Use dm.h header when driver mode is usedSimon Glass1-1/+1
This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10dm: reset: add BCM6345 reset driverÁlvaro Fernández Rojas3-0/+96
This is a simplified version of linux/arch/mips/bcm63xx/reset.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Reset Drivermaxims@google.com3-0/+117
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to perform resets and thus depends on it. The actual Watchdog device used needs to be configured in Device Tree using "aspeed,wdt" property, which must be WDT phandle, for example: rst: reset-controller { compatible = "aspeed,ast2500-reset"; aspeed,wdt = <&wdt1>; } Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-26reset: Add STi reset supportPatrice Chotard3-0/+329
This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. Driver code has been mainly extracted from kernel drivers/reset/sti/reset-stih407.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-02-08dm: core: Replace of_offset with accessorSimon Glass1-2/+2
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-13libfdt: Bring in upstream stringlist functionsSimon Glass1-3/+3
These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-10reset: uniphier: add reset controller driver for UniPhier SoCsMasahiro Yamada3-0/+386
This is the initial commit for UniPhier reset controller driver. Most code was ported from Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-27reset: implement a driver for the Tegra CARStephen Warren3-0/+80
Implement a reset uclass driver for the Tegra CAR. This allows clients to use standard reset APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific reset APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/reset code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15reset: add Tegra186 reset driverStephen Warren3-0/+89
In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-06-20reset: implement a reset testStephen Warren4-0/+173
This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-20Add a reset driver framework/uclassStephen Warren3-0/+151
A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
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