index
:
starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
spi
/
designware_spi.c
Age
Commit message (
Expand
)
Author
Files
Lines
2019-10-24
spi: designware_spi: Disable and free clock when remove driver
Ley Foon Tan
1
-1
/
+15
2019-05-10
spi: designware: convert to livetree
Simon Goldschmidt
1
-6
/
+2
2019-03-04
spi: designware: Change include order
Horatiu.Vultur@microchip.com
1
-1
/
+1
2018-12-19
DW SPI: Allow to overload the management of the external CS
Gregory CLEMENT
1
-1
/
+7
2018-10-02
spi: designware_spi: Add reset ctrl to driver
Ley Foon Tan
1
-0
/
+43
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2018-04-23
spi: dw: invert wait condition in dw_spi_xfer
Eugeniy Paltsev
1
-1
/
+1
2018-03-22
DW SPI: use 32 bit access instead of 16 and 32 bit mix
Eugeniy Paltsev
1
-25
/
+15
2018-03-22
DW SPI: add option to use external gpio for chip select
Eugeniy Paltsev
1
-1
/
+50
2018-03-22
DW SPI: refactor poll_transfer functions
Eugeniy Paltsev
1
-22
/
+4
2018-03-22
DW SPI: fix transmit only mode
Eugeniy Paltsev
1
-1
/
+5
2018-03-22
DW SPI: fix tx data loss on FIFO flush
Eugeniy Paltsev
1
-0
/
+15
2018-01-26
DW SPI: Get clock value from Device Tree
Eugeniy Paltsev
1
-2
/
+43
2017-06-01
dm: Rename dev_addr..() functions
Simon Glass
1
-1
/
+1
2017-02-08
dm: core: Replace of_offset with accessor
Simon Glass
1
-1
/
+1
2015-10-27
spi: designware_spi: Use GENMASK
Jagan Teki
1
-1
/
+1
2015-10-27
spi: designware_spi: Use BIT macro
Jagan Teki
1
-7
/
+7
2015-08-31
dm: Use dev_get_addr() where possible
Simon Glass
1
-1
/
+1
2015-03-29
spi: designware_spi: revisit FIFO size detection again
Axel Lin
1
-2
/
+2
2015-01-30
dm: spi: Move the per-child data size to the uclass
Simon Glass
1
-1
/
+0
2015-01-06
dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi
Marek Vasut
1
-1
/
+1
2015-01-06
spi: designware_spi: Fix detecting FIFO depth
Axel Lin
1
-2
/
+2
2014-12-06
spi: designware_spi: Some fixes / changes
Stefan Roese
1
-19
/
+20
2014-12-06
spi: Add designware master SPI DM driver used on SoCFPGA
Stefan Roese
1
-0
/
+425