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path: root/drivers/spi
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2022-02-05spi: mxc_spi: remove redundant code in spi_xchg_single()Haolin Li1-2/+0
The value of cnt is overwritten without being used. Signed-off-by: Haolin Li <li.haolin@qq.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-30sunxi: SPI: fix pinmuxing for Allwinner H6 SoCsDaniel Wagenknecht1-1/+2
The driver for SPI0 on Allwinner H6 SoCs did not use the correct define SUN50I_GPC_SPI0 for the pin function, but one for a different Allwinner SoC series. Fix the conditionals to use the correct define for H6 SoCs. This matches the conditional logic in the SPL spi driver. Tested by probing the spi-flash on a pine64_h64-model-b board with adapted device-tree (disable mmc2, enable spi0). Signed-off-by: Daniel Wagenknecht <dwagenk@mailbox.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-19doc: replace @return by Return:Heinrich Schuchardt2-4/+4
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-16Fix wrong QSPI clock calculation for AM4372Stefan Mätje1-1/+2
On AM4372 the SPI_GCLK input gets its clock from the PRCM module which divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4. See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration. The QSPI_FCLK therefore needs to take this factor into account and becomes (192000000 / 4). Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
2022-01-09Merge tag 'u-boot-amlogic-20220107' of ↵Tom Rini1-0/+17
https://source.denx.de/u-boot/custodians/u-boot-amlogic into next - disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs - meson64_android: add board specific env settings, in order to support VIM3/L for android - add changes to support VIM3/L android boot by using meson64_android.h config
2021-12-17Merge tag 'u-boot-at91-2022.04-a' of ↵Tom Rini1-25/+572
https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2022.04 cycle: This feature set includes : support for the new QSPI hardware on sama7g5, small fixes on sam9x60 and sama7g5, some additions of commands and PIO controller on sam9x60/sam9x60ek.
2021-12-07spi: atmel-quadspi: Add support for SAMA7G5 QSPITudor Ambarus1-24/+571
sama7g5 QSPI has: 1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported 2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to 90 MHz DDR/133 MHz SDR The QSPI controller of SAMA7G5 uses different clock domains, hence extra synchronization operations must be performed before accessing some registers. Differentiate between the versions of the IP using has_gclk. Differentiate between QSPI0 and QSPI1 with has_octal. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-12-02mtd: cqspi: Wait for transfer completionMarek Vasut1-0/+17
Wait for the read/write transfer finish bit get actually cleared, this does not happen immediately on at least SoCFPGA Gen5. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Pratyush Yadav <p.yadav@ti.com>
2021-11-23spi: atmel-quadspi: Fix QSPI_RD reg name on verbose debugTudor Ambarus1-1/+1
It was wrongly set to "MR", fix it. Fixes: 52e2565bfb ("spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2021-11-16Merge tag 'xilinx-for-v2022.01-rc3' of ↵Tom Rini1-3/+8
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.01-rc3 sdhci: - Fix emmc mini case with missing firmware interface zynqmp: - Restore JTAG interface if required - Allow overriding board name - Add support for DLC21 - Fix one fallthrought statement description - Use config macro instead of name duplication - Save multiboot to variable firmware: - Handle ipi_req errors better - Use local buffer in case user doesn't need it instead of NULL/0 location spi: - gqsi: Fix write issue at low frequencies net: - gem: Disable broadcasts
2021-11-09spi: fsl_dspi: rename num-cs to spi-num-chipselectsMichael Walle1-2/+3
The official devicetree bindings specifies spi-num-chipselects as the name. Use it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspiMichael Walle1-0/+1
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; Add the missing compatible to the driver and update the device tree. We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness is determined by the little-endian property and not by the compatible string itself. Further, we won't need and specific details on the DMA configuration (which is different on the LS1021A). If it's ever needed, we can later add the more specific "fsl,ls1028a-dspi" compatible to the driver. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-10-25spi: zynqmp_gqspi: Fix write issue at low frequenciesAshok Reddy Soma1-3/+8
With current implementation we are seeing write issues at low frequencies below 15Mhz. Make below changes to fix the issue. 1. Remove dummy genfifo entry in zynqmp_qspi_chipselect() which was incorrectly added in the past 2. Enable and poll for TX_FIFO_Empty after Tx data is filled in FIFO in zynqmp_qspi_fill_tx_fifo(). Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1634652780-21755-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-10-23Merge https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini1-9/+68
- Fix mtd erase with mtdpart (Marek Behún) - NXP fspi driver fixes (Kuldeep Singh)
2021-10-23spi: nxp_fspi: Implement errata workaround for LS1028AKuldeep Singh1-5/+48
Errata ERR050568 description says that "Flash access by FlexSPI AHB command may not work with platform frequency equal to 300 MHz" on LS1028A. By default, smaller length reads(equal to RX FIFO size) are done by IP bus and larger length reads using AHB bus. For adding errata workaround, use IP bus to read entire flash contents and disable AHB path when platform frequency is 300Mhz. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23spi: nxp-fspi: Add support for IP read onlyKuldeep Singh1-4/+20
Add support for disabling AHB bus and read entire flash contents via IP bus only. Please note, this enables IP bus read using a quirk which can be enabled directly in device-type data or in existence of an errata where AHB bus may need to be disabled. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-15spi: rockchip_sfc: Using read_pollJon Lin1-32/+35
Using read_poll logic. Tested-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15spi: rockchip_sfc: Implement set_speed logicJon Lin1-43/+39
Set clock related processing into set_speed logic. And Optimize printing format. Tested-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-12Merge tag 'u-boot-stm32-20211012' of ↵Tom Rini1-92/+132
https://source.denx.de/u-boot/custodians/u-boot-stm - Disable ATAGS for STM32 MCU and MPU boards - Disable bi_boot_params for STM32 MCU and MPU boards - Update stm32-usbphyc node management - Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards - Convert some USB config flags to Kconfig for various boards - Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board - Remove specific CONFIG_STV0991 flags - Remove unused CONFIG_USER_LOWLEVEL_INIT flag - Add ofdata_to_platdata() callback for stm32_spi driver - Update for stm32f7_i2c driver - Remove gpio_hog_probe_all() from STM32 MP1 board - Fix bind command Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-11sunxi: gpio: Remove name_to_gpio macroSamuel Holland1-1/+1
This clarifies which callers must be updated to complete the DM_GPIO conversion. The only remaining caller of name_to_gpio in generic code is inside the !DM_GPIO block in cmd/gpio.c. DM_GPIO is always selected on sunxi, so that code cannot be reached. And after this commit, there are only two remaining implementations of name_to_gpio. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-08spi: stm32: Add ofdata_to_platdata() callbackPatrice Chotard1-92/+132
Parse DT in ofdata_to_platdata() callback instead of probe(). Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-10-04Merge branch 'next'Tom Rini12-57/+45
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-04mtd: cqspi: Fix division by zeroMarek Vasut1-0/+3
Both dummy.nbytes and dummy.buswidth may be zero. By not checking the later, it is possible to trigger division by zero and a crash. This does happen with tiny SPI NOR framework in SPL. Fix this by adding the check and returning zero dummy bytes in such a case. Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Pratyush Yadav <p.yadav@ti.com> [trini: Drop Pratyush's RB as his requested changes weren't made as Marek disagreed]
2021-10-02arm: Remove zmx25 board and ARCH_MX25Tom Rini1-8/+1
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last ARCH_MX25 platform, remove those references as well. Cc: Matthias Weisser <weisserm@arcor.de> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01arm: Remove flea3 boardTom Rini1-5/+2
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last mx35 platform, remove that support as well. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefano Babic <sbabic@denx.de>
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk1-1/+1
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-25clk: Rename clk_get_by_driver_info()Simon Glass1-1/+1
This is actually a misnomer now, since the phandle info may contain a driver_info index or a udevice index. Rename it to use the word 'phandle', which seems more accurate. Add a comment while we are here. Also add a test for this function. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Try to avoid the preprocessor with OF_REALSimon Glass2-22/+22
Convert some of these occurences to C code, where it is easy to do. This should help encourage this approach to be used in new code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass4-9/+9
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Simply conditions with the new OF_REALSimon Glass6-11/+11
Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini2-17/+15
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
2021-09-14pci: Drop DM_PCISimon Glass1-1/+1
This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-03spi: zynqmp_gqspi: Fix dma alignment issueAshok Reddy Soma1-9/+7
DMA is aligned to ARCH_DMA_MINALIGN(64 bytes), but as per spec, alignment required is 4bytes only. Change DMA alignment from ARCH_DMA_MINALIGN to GQSPI_DMA_ALIGN. Remove alignment of data length in non-exponential case. Some minor improvements in the initialization to initialize gen_fifo threshold and disable qspi controller while setting config register. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-09-03spi: zynqmp_gqspi: Switch genfifo start to manual modeAshok Reddy Soma1-7/+7
Current implementation uses auto mode for starting generic FIFO. The recommendation from IP designers is to use manual mode, hence change to manual start mode. In fill genfifo first write to genfio and then trigger manual start. Also enable and check for genfifo empty interrupt status in place of genfifo not full interrupt. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-30spi: altera_spi: Do not abuse CONFIG namespaceTom Rini1-4/+2
The value CONFIG_ALTERA_SPI_IDLE_VAL is never re-defined by a board. Rename this to ALTERA_SPI_IDLE_VAL. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-08-18spi: nxp_fspi: Ensure width is respected in spi-mem operationsMichael Walle1-1/+1
Import linux commit 007773e16a6f ("spi: nxp-fspi: Ensure width is respected in spi-mem operations") to fix SPI access on boards which don't have all SPI I/O lines connected to the flash. Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") u-boot figures out the capabilities by looking at spi_mem_supports_op(). The FlexSPI driver doesn't take the board layout into account. Fix that. Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-12spi: rockchip_sfc: add support for Rockchip SFCChris Morgan3-0/+655
This patch adds support for the Rockchip serial flash controller found on the PX30 SoC. It should work for versions 3-5 of the SFC IP, however I am only able to test it on v3. This is adapted from the WIP SPI-MEM driver for the SFC on mainline Linux. Note that the main difference between this and earlier versions of the driver is that this one does not support DMA. In testing the performance difference (performing a dual mode read on a 128Mb chip) is negligible. DMA, if used, must also be disabled in SPL mode when using A-TF anyway. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-03Merge https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini1-4/+6
- SPI-NOR fix (Big Meng) - XMC XM25QH64C flash (Reto Schneider)
2021-08-03spi: spi-mem-nodm: Fix read data size issueBin Meng1-4/+6
When slave drivers don't set the max_read_size, the spi-mem should directly use data.nbytes and not limit to any size. But current logic will limit to the max_write_size. This commit mirrors the same changes in the dm version done in commit 535b1fdb8e5e ("spi: spi-mem: Fix read data size issue"). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-08-02spi: ich: Limit slave->max_read_sizeBin Meng1-2/+4
Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") (in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller in software sequencer mode. ICH controller can only transfer a small number of bytes at once. Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes is limited to slave->max_write_size but after commit 43c145b8b3ee data.nbytes is no longer limited because slave->max_read_size is not initialized with a valid number. Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵Tom Rini2-3/+3
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-15spi: ich: Don't require the PCHSimon Glass1-2/+2
When booting from coreboot we may not have a PCH driver available. The SPI driver can operate without the PCH but currently complains in this case. Update it to continue to work normally. The only missing feature is memory-mapping of SPI-flash contents, which is not essential. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-07-10spi: mxc_spi: fix warnings if CLK_ENABLED not setStefano Babic1-2/+2
Following warnings (unused variables) are raised: drivers/spi/mxc_spi.c: In function 'mxc_spi_probe': drivers/spi/mxc_spi.c:595:14: error: unused variable 'blob' [-Werror=unused-variable] 595 | const void *blob = gd->fdt_blob; | ^~~~ drivers/spi/mxc_spi.c:594:6: error: unused variable 'node' [-Werror=unused-variable] 594 | int node = dev_of_offset(bus); Move the variable declaration inside the code where they are used. Signed-off-by: Stefano Babic <sbabic@denx.de>
2021-07-10spi: fsl_qspi: Build driver only if DM_SPI is availableFrieder Schrempf1-1/+1
The driver depends on DM_SPI and if it's not available (e. g. in SPL), then we should not try to build it as this will fail. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-07-07Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmTom Rini1-0/+2
various minor sandbox improvements
2021-07-06spi: synquacer: Add HSSPI SPI controller driver for SynQuacerJassi Brar3-0/+500
This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-05Merge branch 'next'Tom Rini10-57/+1019
2021-06-30spi: Update speed/mode on changeMarek Vasut1-0/+12
The spi_get_bus_and_cs() may be called on the same bus and chipselect with different frequency or mode. This is valid usecase, but the code fails to notify the controller of such a configuration change. Call spi_set_speed_mode() in case bus frequency or bus mode changed to let the controller update the configuration. The problem can easily be triggered using the sspi command: => sspi 0:0@1000 => sspi 0:0@2000 Without this patch, both transfers happen at 1000 Hz. With this patch, the later transfer happens correctly at 2000 Hz. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-06-29Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-spi ↵Tom Rini9-43/+1004
into next - xSPI Octal DTR support (Pratyush Yadav) - MXIC SPI driver (Zhengxun)
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-05 12:55:53 +0300