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path: root/drivers/spi
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2019-01-28spi: mxc_spi: Fix build warning on ARM64 platformsYe Li1-2/+2
When building mxc_spi driver on ARM64 platforms, get below build warnings. Fix it in this patch. In file included from include/common.h:48:0, from drivers/spi/mxc_spi.c:9: drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’: drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-16mips: spi: mscc: Add fast bitbang SPI driverLars Povlsen3-0/+244
This patch add a new SPI driver for MSCC SOCs that does not sport the designware SPI hardware controller. Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-01spi: sun4i: Add rx_buf NULL pointer checkStefan Mavrodiev1-1/+2
Current driver doesn't check if the destination pointer is NULL. This cause the data from the FIFO to be stored inside the internal SDRAM ( address 0 ). The patch add simple check if the destination pointer is NULL. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Jagan Teki <jagan@openedev.com> [jagan: fix commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-12-19DW SPI: Allow to overload the management of the external CSGregory CLEMENT1-1/+7
On some platforms, as the Ocelot ones, when wanting to control the CS through software, it is not possible to do it through the GPIO controller. Indeed, this signal is managed through a dedicated range of registers inside the SoC.. By declaring the external_cs_manage function as weak, it is possible to manage the CS at platform level and then using the appropriate registers. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-05Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini16-98/+723
- Various MTD fixes from Boris - Zap various unused / legacy paths. - pxa3xx NAND update from Miquel Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-03spi, mpc8xx: migrate to DM_SPIChristophe Leroy1-149/+30
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-11-29spi: cadence_qspi: use "cdns,qspi-nor" as compatibleSimon Goldschmidt1-1/+1
Linux uses "cdns,qspi-nor" as compatible string for the cadence qspi driver, so change driver, docs and all device trees. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-27spi: mpc8xx: Migrate to DM_SPIChristophe Leroy2-155/+36
Drop non-dm code and migrate into DM_SPI. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> [jagan: Move config menu in DM_SPI area] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27spi: Remove unused spi_initJagan Teki11-58/+0
Remove spi_init definition which never used on respective code since from many years. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27dm: platform_data: spi: s/pl022_spi.h/spi_pl022.hJagan Teki1-1/+1
Rename platform_data include file as spi_pl022.h from pl022_spi.h, this is generic notation used for spi platdata include files. Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27spi: pl022: Drop unnecessary include filesJagan Teki1-5/+0
This patch can drop unnecessary include files in pl022_spi driver. Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27spi: pl022: Simplify platdata codeJagan Teki1-28/+20
pl022 spi driver support both OF_CONTROL and PLATDATA, this patch is trying to simplify the code that differentiating platdata vs of_control. - Move OF_CONTROL code at one place - Handle clock setup code directly in pl022_spi_ofdata_to_platdata Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-24spi: mtk_qspi: add qspi driver for MT7629 SoCGuochun Mao3-0/+367
This patch adds MT7629 qspi driver for accessing SPI NOR flash. Signed-off-by: Guochun Mao <guochun.mao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-24spi: Add Amlogic Meson SPI Flash Controller driverNeil Armstrong3-0/+329
The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. This driver, ported from the Linux meson-spi-spifc driver, add support for this controller on the Amlogic Meson GX SoCs in U-Boot. Tested-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-21dm: spi: prevent setting a speed of 0 HzSimon Goldschmidt1-3/+12
When the device tree is missing a correct spi slave description below the bus (compatible "spi-flash" or spi-max-frequency are missing), the 'set_speed' callback can be called with 'speed' == 0 Hz. At least with cadence qspi, this leads to a division by zero. Prevent this by initializing speed to 100 kHz in this case (same fallback value as is done in 'dm_spi_claim_bus') and issue a warning to console. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-16arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek1-2/+2
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-12Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini1-19/+28
2018-10-10spi: davinci: Add platdata supportJagan Teki1-19/+28
Davanci spi driver has DM support already, this patch add support for platdata so-that SPL can use it for low foot-print. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com>
2018-10-09dm: spi: Add logging of some return valuesSimon Glass1-3/+3
When SPI flash operations fail it is helpful to be able to see the error codes and where they are generated. Add logging to capture this information for read operations. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09sandbox: spi: Add more loggingSimon Glass1-29/+9
Add logging to aid debugging features in these drivers. Also drop some code in sandbox_spi_xfer() which is not used. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-04spi: Add SPI driver for MT76xx SoCsStefan Roese3-0/+321
This patch adds the SPI driver for the MediaTek MT7688 SoC (and derivates). Its been tested on the LinkIt Smart 7688 and the Gardena Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart Gateway additionally with an SPI NAND on CS1. Note that the SPI controller only supports a max transfer size of 32 bytes. This driver implementes a workaround to enable bigger xfer sizes to speed up the transfer especially for the SPI NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Piotr Dymacz <pepe2k@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-10-03Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini6-203/+702
This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-02spi: sh_qspi: Add DM support to SH QSPI driverMarek Vasut1-65/+150
Add DM support to the SH QSPI driver while retaining non-DM support. The later is required as this driver is used in SPL which has a size limitation of 16 kiB. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> [jagan: use proper commit head] Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-02driver/spi: fsl_qspi: Remove non-DM stuffAshish Kumar1-138/+0
Convert fsl_qspi.c to complete DM mode. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Tested-by: Rajat Srivastava <rajat.srivastava@nxp.com> Tested-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-02spi: designware_spi: Add reset ctrl to driverLey Foon Tan1-0/+43
Add code to reset all reset signals as in SPI DT node. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Release reset when _remove(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-09-26spi: add support for ARM PL022 SPI controllerQuentin Schulz3-0/+347
This adds support for the ARM PL022 SPI controller for the standard variant (0x00041022) which has a 16bit wide and 8 locations deep TX/RX FIFO. A few parts were borrowed from the Linux kernel driver. Cc: Armando Visconti <armando.visconti@st.com> Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-20spi: Extend the core to ease integration of SPI memory controllersBoris Brezillon3-0/+509
Some controllers are exposing high-level interfaces to access various kind of SPI memories. Unfortunately they do not fit in the current spi_controller model and usually have drivers placed in drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI memories in general. This is an attempt at defining a SPI memory interface which works for all kinds of SPI memories (NORs, NANDs, SRAMs). Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-08-03arm: sunxi: Allwinner A10 SPI driverStefan Mavrodiev3-0/+462
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is adapted from mailine kernel. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-08-03spi: kirkwood: add orion-spi compatible stringChris Packham1-0/+8
This matches the compatible string used by the Linux kernel. This will allow u-boot to use the same device tree files. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: use armada instead of orion on .data] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-08-03spi: kirkwood: Get drvdata in .ofdata_to_platdataJagan Teki1-3/+5
Get the is_errata_50mhz_ac in .ofdata_to_platdata, and reuse it in .set_mode this can eventually initialized dt code at once and adding room to add platdata. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-23spi: stm32_qspi: rework mode managementChristophe Kerello1-14/+14
This patch solves quad read issue with Macronix/Micron spi nor. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-23spi: stm32_qspi: assign functional operation mode in _stm32_qspi_gen_ccrChristophe Kerello1-9/+8
This patch assigns the functional operation mode in _stm32_qspi_gen_ccr function. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-16spi: zynqmp_gqspi: Add support for ZynqMP qspi driverSiva Durga Prasad Paladugu3-0/+737
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> [jagan: removed GQSPI_MIO_NUM_ macros] Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: convert to livetreeVipul Kumar1-3/+2
Update the xilinx spi driver to support a live tree. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: Added support to read JEDEC-id twice at the boot timeVipul Kumar1-0/+41
This patch is for the startup block issue in the spi controller. SPI clock is passing through STARTUP block to FLASH. STARTUP block don't provide clock as soon as QSPI provides command. So, first command fails. This patch added support to read JEDEC id in xilinx_spi_xfer (). Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() functionVipul Kumar1-35/+68
This patch modify xilinx_spi_xfer() function and add rxfifo() and txfifo() functions to add the modularity so that these functions can be used by other functions within the same file. This patch also added support to read fifo_size from dts. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx: Read reg base address from DTS fileMichal Simek1-6/+1
This patch added support to read register base address from DTS file. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-12spi: cadence_qspi: Fix warning cast from pointer to integer of different sizeLey Foon Tan1-2/+2
Use "%p" to print cmdbuf. Compilation warning as below: CC spl/drivers/spi/cadence_qspi_apb.o LD spl/lib/built-in.o drivers/spi/cadence_qspi_apb.c: In function ‘cadence_qspi_apb_indirect_write_setup’: drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] cmdlen, (unsigned int)cmdbuf); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
2018-07-12spi: cadence_qspi: Fix compilation warningLey Foon Tan1-1/+1
Use "%zu" for size_t data type. Compilation warning as below: In file included from include/linux/bug.h:7:0, from include/common.h:26, from drivers/spi/cadence_qspi.c:8: drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’: drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’ [-Wformat=] debug("%s: len=%d [bytes]\n", __func__, data_bytes); ^ include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’ #define pr_fmt(fmt) fmt ^~~ include/log.h:142:2: note: in expansion of macro ‘debug_cond’ debug_cond(_DEBUG, fmt, ##args) ^~~~~~~~~~ drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’ debug("%s: len=%d [bytes]\n", __func__, data_bytes); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
2018-07-10board: arm: Add support for Broadcom BCM7445Thomas Fitzsimmons4-1/+448
Add support for loading U-Boot on the Broadcom 7445 SoC. This port assumes Broadcom's BOLT bootloader is acting as the second stage bootloader, and U-Boot is acting as the third stage bootloader, loaded as an ELF program by BOLT. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Florian Fainelli <f.fainelli@gmail.com>
2018-06-28spi: omap3: fix claim/release bus within DMHannes Schmelzer1-7/+7
The claim/release bus function must not reset the whole SPI core because settings regarding wordlen, clock-frequency and so on made by set_wordlen, set_mode, set_speed get lost with this action. Resulting in a non-functional SPI. Without DM the failure didn't came up since after the spi_reset within claim bus all the setup (wordlen, mode, ...) was called, in DM they are called by the spi uclass. We change now the things as following for having a working SPI instance in DM: - move the spi_reset(...) to the probe call in DM for having a known hardware state after probe. Without DM we don't have a probe call, so we issue the reset as before during the claim_bus call. - in release bus we just reset the modulctrl to the reset-value (spi- slave) Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25spi: omap3: fix set_speed and set_mode dm callbacksHannes Schmelzer1-10/+6
commit 84807922874e03895bbf15c4472a2dcee8fbbd03 ("spi: omap3: Skip set_mode, set_speed from claim") did break SPI support on my AM335x board. The named commit: - ignored the responsible arguments (speed, mode) The set speed/mode function must use the supplied function arguments to work properly. With this commit we take those arguments and transfer them to the priv-data. - used wrong udevice pointer for getting priv data the udevice-pointer within function argument is already the spi-bus device, so it is wrong looking here for some parent (ocp-bus in this case) and getting priv-pointer from there. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25spi: omap3: pre-initialize bus-speed with max. slave-speedHannes Schmelzer1-0/+2
Otherwise the frequency is zero and the clock divider cannot be setup by 'omap3_spi_set_speed' function. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25spi: mxc_spi: Fix chipselect on DM_SPI driver uclassMichael Trimarchi1-3/+3
CS GPIO activation low/high is determinated by the device tree so we don't need to take in accoung in cs_activate and cs_deactivate Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25spi: mxc: Fix compilation problem of DM_SPI class driverMichael Trimarchi1-1/+1
drivers/spi/mxc_spi.c:507: undefined reference to `dev_get_addr' linux-ld.bfd: BFD (GNU Binutils) 2.29.1 assertion fail elf32-arm.c:9509 Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25spi: zynq_qspi: Fixed incorrect return value errorVipul Kumar1-1/+1
This patch replaced "return 0" with "return status" to fix the incorrect return value error reported by the coverity. Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> [jagan: rebased on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-06-04spi: cadence_qspi: Change to use devfdt_get_addr_index()Ley Foon Tan1-11/+2
Change to use devfdt_get_addr_index() function to get fdt address. Original code has compilation warning below: drivers/spi/cadence_qspi.c: In function ‘cadence_spi_ofdata_to_platdata’: drivers/spi/cadence_qspi.c:297:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] plat->regbase = (void *)data[0]; ^ drivers/spi/cadence_qspi.c:298:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] plat->ahbbase = (void *)data[2]; ^ Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-01Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2-18/+6
2018-06-01spi: bcm63xx_hsspi: convert to use live dtÁlvaro Fernández Rojas1-9/+3
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01spi: bcm63xx_spi: convert to use live dtÁlvaro Fernández Rojas1-9/+3
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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