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path: root/drivers/sysreset/Makefile
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2021-10-07sysreset: provide SBI based sysreset driverHeinrich Schuchardt1-0/+1
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2020-11-01sysreset: Add poweroff-gpio driverSebastian Reichel1-0/+1
Add GPIO poweroff driver, which is based on the Linux driver and uses the same DT binding. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2020-10-09sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64Chee Hong Ang1-1/+1
Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-07-18sysreset: Add Octeon sysreset driverStefan Roese1-0/+1
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC family. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-04-27sysreset: add reset controller based reboot driverWeijie Gao1-0/+1
Some chips provide their sysreset function in reset controller, which is normally a bit written to 1 to perform the sysreset. This patch adds a new sysreset driver to take advantage of it. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-12-13sysreset_mpc83xx: fix mcp83xx -> mpc83xx typoRasmus Villemoes1-1/+1
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-10-08x86: sysreset: Allow reset driver to be included in SPL/TPLSimon Glass1-1/+1
At present this driver is always included in SPL and TPL, if U-Boot proper enables it. Update the Makefile to provide full control using the existing Kconfig options. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: make the Kconfig help text a little bit clearer] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-21sysreset: socfpga: stratix10: add sysreset driverSimon Goldschmidt1-0/+1
This adds a UCLASS_SYSRESET sysreset driver for socfgpa stratix10. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-07-21sysreset: socfpga: gen5: add sysreset driverSimon Goldschmidt1-0/+1
This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-08sysreset: enable driver support in SPL/TPLKever Yang1-1/+1
SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2018-09-18mpc83xx: Add sysreset driverMario Six1-4/+5
Add a sysreset driver for the MPC83xx platform. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-11sysreset: Add TI System Control Interface (TI SCI) sysreset driverAndreas Dannenberg1-0/+1
Devices from the TI K3 family of SoCs like the AM654x contain a Device Management and Security Controller (SYSFW) that manages the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a system reset driver that communicates to the system controller over the TI SCI protocol for allowing to perform a system- wide SoC reset. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-07-20dm: sysreset: x86: Add a sysreset driverBin Meng1-0/+1
This adds a generic reset driver for x86 processor. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19sysreset: Add support for Microblaze soft reset jumpMichal Simek1-0/+1
Microblaze is storing reset vector at address 0x0. It means soft reset can be done by just jumping to this address. This code was in platform code but sysreset interface is providing enough capabilities to have more options how to reset the system. It can go from gpio reset through watchdog reset till soft reset. The driver has not compatible string because this is cpu specific and DM core is not able to detect compatible string in DT root that's why this driver will be instantiated from platform code by calling device_bind_driver(gd->dm_root, "mb_soft_reset", "reset_soft", NULL); It should be bind as the last reset method to ensure that hw reset is called before this. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19sysreset: Add support for gpio-restartMichal Simek1-0/+1
The Linux kernel has binding for gpio-restart node. This patch is adding basic support without supporting any optional properties. This driver was tested on Microblaze system where gpio is connected to SoC reset logic. Output value is handled via gpios cells values. In gpio_reboot_request() set_value is writing 1 because dm_gpio_set_value() is capable to changing it when it is ACTIVE_LOW. ... if (desc->flags & GPIOD_ACTIVE_LOW) value = !value; ... Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-3/+1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-16db410c: replace reset driver with psciJorge Ramirez-Ortiz1-2/+0
this should be the norm for armv8 platforms. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-11-22rockchip: sysreset: update Makefile to work with merged sysreset driverPhilipp Tomsich1-10/+1
After applying the merged sysreset driver, there are build failures due to an out-of-sync Makefile. This updates drivers/sysreset/Makefile to address these build failures. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: enable rk322x sysreset driverKever Yang1-0/+1
The sysreset driver for rk322x is ready but not enabled, add it to Makefile to make sure it's enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-07rockchip: Add core Soc start-up code for rv1108Andy Yan1-0/+1
RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core from Rockchip. It is designed for varies application scenario such as car DVR, sports DV, secure camera and UAV camera. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07rockchip: rk3368: Add sysreset driverAndy Yan1-0/+1
Add sysreset driver to reset rk3368 SOC. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-31dm: sysreset: add watchdog-reboot driverÁlvaro Fernández Rojas1-0/+1
Add a new sysreset driver that uses the recently added watchdog support. It performs a full SoC reset by calling wdt_expire_now op. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10sysreset: add syscon-reboot driverÁlvaro Fernández Rojas1-0/+1
Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c, which provides a generic driver for platforms that only require writing a mask to a regmap offset. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-18sysreset: psci: support system reset in a generic way with PSCIMasahiro Yamada1-0/+1
If the system is running PSCI firmware, the System Reset function (func ID: 0x80000009) is supposed to be handled by PSCI, that is, the SoC/board specific reset implementation should be moved to PSCI. U-Boot should call the PSCI service according to the arm-smccc manner. The arm-smccc is supported on ARMv7 or later. Especially, ARMv8 generation SoCs are likely to run ARM Trusted Firmware BL31. In this case, U-Boot is a non-secure world boot loader, so it should not be able to reset the system directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-17rockchip: rk3328: add sysreset driverKever Yang1-0/+1
Add rk3328 sysreset driver. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-17rockchip: rk3188: Add sysreset driverHeiko Stübner1-0/+1
Driver for the sysreset of Rockchip rk3188 socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-15STiH410: Add STi sysreset driverPatrice Chotard1-0/+1
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-28aspeed: Add drivers common to all Aspeed SoCsmaxims@google.com1-0/+1
Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-16xtensa: add support for the 'xtfpga' evaluation boardChris Zankel1-0/+1
The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-12drivers/sysreset: group sysreset driversMax Filippov1-0/+15
Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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