summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2020-01-07clk: agilex: Add clock driver for AgilexLey Foon Tan3-0/+817
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan1-1/+1
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move firewall code to firewall fileLey Foon Tan1-1/+1
Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert clock manager from struct to definesLey Foon Tan1-7/+4
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan5-22/+13
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert reset manager from struct to definesLey Foon Tan1-3/+3
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07spl: Allow cache drivers to be used in SPLLey Foon Tan2-1/+2
Add an option for building cache drivers in SPL. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07Merge branch 'next'Tom Rini78-408/+4034
Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
2020-01-04Revert "mmc: davinci: drop struct davinci_mmc_plat"Tom Rini1-5/+11
Adam Ford reports that this change breaks booting on da850-evm and Bartosz Golaszewski agrees that with the impending release we should revert the change for now. With that noted: This reverts commit 21a4d80a710c79053ac1deaa65ff9b69e6c031d4. Cc: Bartosz Golaszewski <brgl@bgdev.pl> Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-02video: add wrappers for ttf type files to .gitignoreDario Binacchi1-0/+1
The scripts/Makefile.lib generates an assembler file (*.S) to wrap the font data for each file of type ttf defined in Kconfig. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-01-02video: Avoid using #ifdef in video-uclass.cSimon Glass1-28/+26
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use IS_ENABLED(), etc., instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: Avoid using #ifdef in vidconsole-uclass.cSimon Glass1-12/+10
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use CONFIG_IS_ENABLED() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: Avoid using #ifdef in console_rotate.cSimon Glass1-167/+158
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use IS_ENABLED() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: Avoid using #ifdef in video blitting codeSimon Glass1-64/+61
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use IS_ENABLED() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: x86: Enable 32-bit graphics by defaultSimon Glass1-4/+1
Most x86 boards that use video make use of 32bpp graphics. Enable this by default. This fixes missing graphics output on some x86 boards. Also remove the unnecessary 'default n' while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02pci: layerscape: Manage PCIe EP compatible string via KconfigPankaj Bansal3-2/+11
The ep node device tree name is governed by these bindings: https://github.com/torvalds/linux/blob/master/Documentation/ devicetree/bindings/pci/layerscape-pci.txt#L24 As per above the ep compatible node contains platform name. Therefore, define the ep node compatible as CONFIG to find the pcie ep node in device tree during device tree fixup. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02pci: layerscape: move PCIE related CONFIG to PCI KconfigPankaj Bansal1-0/+15
move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-28Merge tag 'u-boot-imx-20191228' of ↵Tom Rini3-4/+7
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - Fixes for Nitrogen6x - Fix corruption for mx51evk - colibri i.MX6: fix broken ESDHC conversion - mx6sxsabresd: fix broken mmcdev - imx6q_logic: cleanup boot sequence - update ATF for imx8mq_evk - pfuze: fix pmic_get() Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
2019-12-28Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini3-2/+19
- rk spi transfer limit fix - Gigadevice, gd25q128 support - spi-nor-core warnings
2019-12-27rtc: rx8010js: add compatible stringRobert Beckett1-0/+1
Add compatible string used by Linux. Allows for simpler syncing of device trees. Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27rtc: s35392a: add compatible stringsRobert Beckett1-0/+2
Add compatible strings used by Linux. Allows for simpler syncing of device trees. Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27rtc: rx8010sj: fix DM initializationRobert Beckett1-1/+1
pass the udevice by reference instead of double ref Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27spi: rk: Limit transfers to (64K - 1) bytesJagan Teki1-2/+8
The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang. Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff. Note, that the size is further divided into 'minus 1' while writing into CTRLR1. This change fixed two different read issues, 1. sf read failure when with > 0x10000 2. Boot from SPI flash failed during spi_flash_read call in common/spl/spl_spi.c Observed and Tested in - Rockpro64 with Gigadevice flash - ROC-RK3399-PC with Winbond flash Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27mtd: spi-nor-core: Fix static checker warningsVignesh Raghavendra1-0/+6
Static checker warns 'ret' variable may be used uninitialized in spi_nor_erase() and spi_nor_write() in case of zero length requests. Fix these warnings by checking for zero length requests and returning early. Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-27imx8m: ddr_init: Move ddr_init() messages to debug levelFabio Estevam1-3/+3
Currently inside ddr_init() there is a mix of printf() and debug() level messages. Since this type of information is useful for debug purposes, convert all of them to debug level for consistency. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-12-26phy: ti-pipe3: Fix SATA & USB PHY power up sequenceRoger Quadros1-17/+19
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: improve DPLL stability for SATA & USBRoger Quadros1-0/+193
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: Introduce mode property in driver dataRoger Quadros1-6/+28
Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: Use TRM recommended settings for SATA DPLLRoger Quadros1-7/+7
The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26armv8: lx2160a: Add FSL_PEX_STREAM_ID_END for LX2160AWasim Khan1-1/+1
Add FSL_PEX_STREAM_ID_END and remove FSL_PEX_STREAM_ID_NUM for lx2160a. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26pci: layerscape_gen4: Suffix API names with _ls_gen4Wasim Khan1-8/+12
Update API names for layerscape gen4 fixup. Suffix layerscape_gen4 fixup API names with _ls_gen4. This is required to organize device tree fixup in common, layerscape and layerscape_gen4 specific code. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26pci: layerscape: Suffix API names with _lsWasim Khan1-11/+11
Suffix layerscape fixup API names with _ls. This is required to organize device tree fixup in common, layerscape and layerscape_gen4 specific code. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26pci: layerscape: Add stream_id_cur field to ls_pcie structureWasim Khan2-2/+4
Add stream_id_cur field to ls_pcie structure and initialize it with 0 for all pcie controllers. This field will be used for streamId calculation. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26drivers/pci : enable pcie_layerscape code for lx2160a rev2Wasim Khan1-1/+1
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses pcie_layerscape driver. Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4. Based on SoC and revision pcie controller probe will be invoked. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26drivers/fsl-mc: Support DPSPARSER object and apply spb commandFlorinel Iordache4-22/+396
Add support for DPSPARSER object (create/destroy, open/close, apply spb) which is required to configure Soft Parser by using MC. Also add uboot command to apply Soft Parser Blob with command: fsl_mc apply spb <spb_load_addr> Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23mpc85xx: ddr: Always start DDR RAM in Self Refresh modeJoakim Tjernlund1-7/+6
Some of t1042 boards fails DDR init with an Automatic calibration error every now and then. Investigations revealed that true Warm boots never failed. Warm boots has some extra steps performed, one being to start DDRC in Self Refresh and then clearing SR right after. Applying this SR method unconditionally made all our boards stable again, regardless of Cold/Warm boot. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-22Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini3-16/+17
- dwc3 and cdns3 bug fixes
2019-12-21usb: dwc3: Fix UTMI/UTMIW phy interface initializationJagan Teki2-16/+16
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-21usb: cdns3: ep0: Fix build warnings related to cache opsVignesh Raghavendra1-0/+1
Since, commit 62f9b6544728 ("common: Move older CPU functions to their own header") cache ops functions are declared in a separate header. Include the same to avoid build warnings. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-20drivers: net: bcm-sf2: pass -1 to phy_connect()Alex Marginean1-1/+1
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or is scanning the bus, passing -1 here should keep it functional either way. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Cc: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-20net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYsMarek Vasut1-1/+1
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to phy_connect(). Passing 0 used to work before be accident, but does no longer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-18mtd: spi-nor: ids: Add GigaDevice gd25q128Peter Robinson1-0/+5
Add gd25q128 128Mbit chip to spi-nor id table. Tested on Pinebook Pro Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 ↵Tom Rini63-307/+3263
into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral
2019-12-17misc: i2c_eeprom: add size queryRobert Beckett1-19/+126
Add ability to query size of eeprom device and partitions Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17misc: i2c_eeprom: add fixed partitions supportRobert Beckett1-0/+98
Add ability to partition eeprom via devicetree bindings Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17dm: i2c: EEPROM simulator add tests for addr offset maskRobert Beckett1-5/+14
Add support for setting the chip address offset mask to EEPROM sumulator and add tests to test it. Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17dm: i2c: EEPROM simulator allow tests visibility of addr and offsetRobert Beckett1-14/+47
Improve i2c EEPROM simulator testing by providing access functions to check the previous chip addr and offset. Given that we can now directly test the offsets, also simplified the offset mapping and allow for wrapping acceses. Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17i2c: add support for offset overflow in to addressRobert Beckett1-7/+27
Some devices (2 wire eeproms for example) use some bits from the chip address to represent the high bits of the offset instead of or as well as using multiple bytes for the offset, effectively stealing chip addresses on the bus. Add a chip offset mask that can be set for any i2c chip which gets filled with the offset overflow during offset setup. Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Ian Ray <ian.ray@ge.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-15i2c: designware: Add Apollo Lake supportSimon Glass1-0/+25
For Apollo Lake we need to take the I2C bus controller out of reset before using this. Add this functionality to the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add pinctrl driverSimon Glass3-3/+206
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-02 17:07:24 +0300