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2022-02-15starfive: add ID_EEPROM supoort for visionfive V1Wei Fu1-2/+1
This patch add ID_EEPROM (mac command) support for visionfive V1. Signed-off-by: Wei Fu <wefu@redhat.com>
2022-02-15drivers/net/phy/marvell: setup LED config for JH7100 EVBYanhong Wang1-0/+14
2022-02-15starfive: Modify designware driver for JH7100Bo Li3-13/+60
This patch is using internal RAM to improve performance （avoid flushing L2 cache): Modify designware driver by: 1, Modify gtxclk configuration by phydev->speed 2, Add Preseted mem support for mac descrtables and buffs 3, disable DMA memory range check when building for JH7100
2022-02-15starfive: Add JH7100 MMC driver supportWei Fu3-0/+176
This driver modified from snps_dw_mmc.c Signed-off-by: Wei Fu <wefu@redhat.com>
2022-02-15starfive: add JH71x0 serial driverWei Fu3-0/+354
This driver ported from NS16550 Serial Port driver, It is a simplified version of drivers/serial/ns16550.c We may can merge it to ns16550 later. Signed-off-by: Wei Fu <wefu@redhat.com>
2022-02-15starfive: add OTP driver for jh7100Yanhong Wang3-0/+218
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2022-02-15sifive: make WayEnable can be configured by menuconfigWei Fu2-0/+16
Signed-off-by:Wei Fu <wefu@redhat.com>
2022-02-15sifive_cache: add flush_range func in sifive cache driverWei Fu1-1/+60
Signed-off-by: Wei Fu <wefu@redhat.com>
2022-02-15cache: add flush_range interface in cache_ops structWei Fu1-0/+11
Signed-off-by: Wei Fu <wefu@redhat.com>
2022-02-15net/phy: add YuTai Corp Ethernet PHYs(YT8511/YT8521) driverWalker Chen4-0/+289
This pathch adds YuTai Corp Ethernet PHYs(YT8511/YT8521) support. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-02-11phy: nop-phy: Enable reset-gpios supportAdam Ford1-3/+42
Some usb-nop-xceiv devices use a gpio take them out of reset. Add a reset function to put them into that state. This is similar to how Linux handles the usb-nop-xceiv driver. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-11DFU: Check the number of arguments and argument string strictlyMasami Hiramatsu7-97/+133
When parsing the dfu_alt_info, check the number of arguments and argument string strictly. If there is any garbage data (which is not able to be parsed correctly) in dfu_alt_info, that means something wrong and user may make a typo or mis- understanding about the syntax. Since the dfu_alt_info is used for updating the firmware, this mistake may lead to brick the hardware. Thus it should be checked strictly for making sure there is no mistake. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2022-02-11DFU: Accept redundant spaces and tabs in dfu_alt_infoMasami Hiramatsu6-14/+37
If dfu_alt_info has repeated spaces or tab (for indentation or readability), the dfu fails to parse it. For example, if dfu_alt_info="mtd nor1=image raw 100000 200000" (double spaces after "raw"), the image entity start address is '0' and the size '0x100000'. This is because the repeated space is not skipped. Use space and tab as a separater and apply skip_spaces() to skip redundant spaces and tabs. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2022-02-11DFU: Do not copy the entity name over the buffer sizeMasami Hiramatsu1-1/+1
Use strlcpy() instead of strcpy() to prevent copying the entity name over the name buffer size. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2022-02-11button: adc: set state to pressed when the voltage is closest to nominalPeter Cai1-5/+16
In the Linux implementation of adc-keys (drivers/input/keyboard/adc-keys.c), `press-threshold-microvolt` is not really interpreted as a threshold, but rather as the "nominal voltage" of the button. When the voltage read from the ADC is closest to a button's `press-threshold-microvolt`, the button is considered pressed. This patch reconciles the behavior of button-adc with Linux's adc-keys such that device trees can be synchronized with minimal modifications. Signed-off-by: Peter Cai <peter@typeblog.net>
2022-02-11Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini2-6/+22
2022-02-11usb: gadget: ci: Avoid null pointer dereferenceMarek Vasut1-1/+4
The ci_req->hw_buf can be NULL, test whether it is and if so, avoid accessing it. Else, the system may crash. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peter Chen <peter.chen@nxp.com> Cc: Li Jun <jun.li@nxp.com> Cc: Peng Fan <peng.fan@nxp.com>
2022-02-11usb: ehci-mx6: Enable OTG detection on imx8mm and imx8mnAdam Ford1-5/+18
The imx8mm and imx8mn appear compatible with imx7d-usb flags in the OTG driver. If the dr_mode is defined as host or peripheral, the device appears to operate correctly, however the auto host/peripheral detection results in an error. The solution isn't just adding checks for imx8mm and imx8mn to the check for imx7, because the USB clock needs to be running to read from the USBNC_PHY_STATUS_OFFSET register or it will hang. Marek requested that I not enable the clocks in ehci_usb_of_to_plat, so I modified that function to return an unknown state if the device tree does not explicitly state whether it is a host or a peripheral. When the driver probes, it looks to see if it's in the unknown state, and only then will it read the register to auto-detect. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Tim Harvey <tharvey@gateworks.com>
2022-02-11input: apple: Add support for Apple SPI keyboardMark Kettenis3-0/+280
This driver adds support for the keyboard on Apple Silicon laptops. The controller for this keyboard sits on an SPI bus and uses an Apple-specific HID over SPI protocol. The packets sent by this controller for key presses and key releases are fairly simple and are decoded directly by the code in this driver and converted into standard Linux keycodes. The same controller handles the touchpad found on these laptops. Packets for touchpad events are simply ignored. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-11spi: apple: Add driver for Apple SPI controllerMark Kettenis3-0/+293
Add a driver for the SPI controller integrated on Apple SoCs. This is necessary to support the keyboard on Apple Silicon laopts since their keyboard uses an Apple-specific HID over SPI protocol. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-11nvme: apple: Add driver for Apple NVMe storage controllerMark Kettenis3-0/+252
Add a driver for the NVMe storage controller integrated on Apple SoCs. This NVMe controller isn't PCI based and deviates from the NVMe standard in its implementation of the command submission queue and the integration of an NVMMU that needs to be managed. This commit tweaks the core NVMe code to support the linear command submission queue implemented by this controller. But setting up the submission queue and managing the NVMMU controller is handled by implementing the driver ops that were added in an earlier commit. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Tested-on: firefly-rk3399 Tested-by: Mark Kettenis <kettenis@openbsd.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-11power: domain: apple: Add reset supportMark Kettenis1-1/+72
The power management controller found on Apple SoCs als provides a way to reset all devices within a power domain. This is needed to cleanly shutdown the NVMe controller before we hand over control to the OS. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-11nvme: Add shutdown functionMark Kettenis2-0/+19
Add a function to disable the NVMe controller. This will be used to let the driver for the NVMe storage integrated on Apple SoCs shutdown the NVMe controller such we can shutdown the NVMe IOP controller in a clean way afterwards before handing control to the OS. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-11nvme: Introduce driver opsMark Kettenis2-27/+73
The NVMe storage controller integrated on Apple SoCs deviates from the NVMe standard in two aspects. It uses a "linear" submission queue and it integrates an NVMMU that needs to be programmed for each NVMe command. Introduce driver ops such that we can set up the linear submission queue and program the NVMMU in the driver for this strange beast. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-11mailbox: apple: Add driver for Apple IOP mailboxMark Kettenis3-0/+104
This mailbox driver provides a communication channel with the Apple IOP controllers found on Apple SoCs. These IOP controllers are used to implement various functions such as the System Manegement Controller (SMC) and NVMe storage. It allows sending and receiving a 96-bit message over a single channel. The header file with the struct used for mailbox messages is taken straight from Linux. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Sven Peter <sven@svenpeter.dev> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-11nvme: Split out PCI supportMark Kettenis5-36/+65
Apple SoCs have an integrated NVMe controller that isn't connected over a PCIe bus. In preparation for adding support for this NVMe controller, split out the PCI support into its own file. This file is selected through a new CONFIG_NVME_PCI Kconfig option, so do a wholesale replacement of CONFIG_NVME with CONFIG_NVME_PCI. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-10Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini3-0/+187
2022-02-10Merge tag 'dm-pull-8feb22-take3' of ↵Tom Rini2-6/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-dm patman snake-case conversion binman fit improvements ACPI fixes and making MCFG available to ARM [trini: Update scripts/pylint.base] Signed-off-by: Tom Rini <trini@konsulko.com>
2022-02-10serial: Add RISC-V HTIF console driverAnup Patel3-0/+187
Quite a few RISC-V emulators and ISS (including Spike) have host transfer interface (HTIF) based console. This patch adds HTIF based console driver for RISC-V platforms which depends totally on DT node for HTIF register base address. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2022-02-09serial-uclass: fix build warningHeiko Schocher1-1/+1
if CONFIG_DM_STDIO is defined but SERIAL_PRESENT not, gcc drops warnings for serial_stub_* functions that they are defined but not used. Fix it. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09serial: remove nulldev_serial_inputHeiko Schocher1-5/+0
nulldev_serial_input is static and not used in this file, so remove it. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini1-3/+2
- Fix an issue with fsl_esdhc_imx - Consider GP partitions in "mmc hwpartition user enh start -"
2022-02-09Convert CONFIG_SCSI_AHCI_PLAT et al to KconfigSimon Glass3-0/+42
This converts the following to Kconfig: CONFIG_SCSI_AHCI_PLAT CONFIG_SYS_SCSI_MAX_SCSI_ID CONFIG_SYS_SCSI_MAX_LUN CONFIG_SYS_SATA_MAX_DEVICE Drop CONFIG_SCSI for everything except the sandbox build. We only need one build for tests. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09scsi: Drop CONFIG_SYS_SCSI_MAX_DEVICESimon Glass1-3/+3
This is defined based on two other CONFIGs for all boards except sandbox and durian. For sandbox the value does not matter. For durian the value seems excessive. Drop the option completely, to simplify configuration and reduce the number of things we need to convert to Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09ahci: Make ahci drivers depend on AHCISimon Glass1-13/+13
At present all ahci drivers depend on AHCI except for DWC_AHCI. But no boards enable that without also enabling AHCI: /tools/moveconfig.py -f ~AHCI DWC_AHCI 0 matches Group them together and sort them in order by Kconfig name (except for AHCI_MVEBU which uses a different naming convention). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: sata_sil: Only support BLKSimon Glass1-115/+3
No boards use this driver without CONFIG_BLK, so clean up the dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Rearrange Kconfig for SATASimon Glass1-34/+37
Move the SATA options inside an 'if SATA' part, so they are grouped. Fix the 'Complient' typo while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Only support BLKSimon Glass2-30/+1
No boards currently use SATA without BLK: ./tools/moveconfig.py -f SATA ~BLK 0 matches Make SATA depend on BLK to avoid any future confusion. Drop the dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Drop Silicon Image SIL3114 SATA driverSimon Glass4-978/+0
This is not used in U-Boot and has not been converted to driver model. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09Convert CONFIG_SYS_IDE_MAXBUS et al to KconfigSimon Glass1-0/+104
This converts the following to Kconfig: CONFIG_SYS_IDE_MAXBUS CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ATA_STRIDE CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_ALT_OFFSET CONFIG_SYS_ATA_IDE0_OFFSET CONFIG_SYS_ATA_IDE1_OFFSET CONFIG_ATAPI CONFIG_IDE_RESET Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09ide: Drop CONFIG_IDE_AHBSimon Glass1-22/+0
This is not used in U-Boot anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09mmc: fsl: Use brackets around if()Simon Glass1-1/+1
At present the IS_ENABLED() macro has extra brackets, making it possible to write: if IS_ENABLED(CONFIG_XXX) but it is a bit confusing. Add the missing brackets. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-09mmc: fsl_esdhc_imx: fix watermark level in dmaMarcel Ziswiler1-3/+2
Seems that we need the waterlevel setting not only for PIO mode as without this at least the i.MX 8M Mini won't boot anymore when being written by such a U-Boot. Corruption has also been observed both on the i.MX 6 as well as i.MX 8M Mini when using ums on the eMMC. Fix this by setting the watermark level again regardless of whether in DMA or PIO mode. Fixes: 41c6a22fc296 ("mmc: fsl_esdhc_imx: simplify esdhc_setup_data()") Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Tested-by: Fabio Estevam <festevam@gmail.com>
2022-02-08phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju1-16/+42
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade1-1/+377
Add register sequences for PCIe + QSGMII PHY multilink configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade1-8/+145
Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade1-3/+215
Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade1-1/+40
PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-0/+35
Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade1-0/+38
Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-02 22:40:05 +0300