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2019-07-27remoteproc: tisci: add TI-SCI processor control helper functionsLokesh Vutla1-0/+121
Texas Instruments' K3 generation SoCs has specific modules/register spaces used for configuring the various aspects of a remote processor. These include power, reset, boot vector and other configuration features specific to each compute processor present on the SoC. These registers are managed by the System Controller such as DMSC on K3 AM65x SoCs. The Texas Instrument's System Control Interface (TI-SCI) Message Protocol is used to communicate to the System Controller from various compute processors to invoke specific services provided by the firmware running on the System Controller. Add a common processor control interface header file that can be used by multiple remoteproc drivers. The helper functions within this header file abstract the various TI SCI protocol ops for the remoteproc drivers, and allow them to request the System Controller to be able to program and manage various remote processors on the SoC. The common macros required by the R5 remoteproc driver were also added. The remoteproc drivers are expected to manage the life-cycle of their ti_sci_proc_dev local structures. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2019-07-27power: domain: ti_sci_power_domains: Add support for exclusive and shared accessLokesh Vutla1-1/+30
TISCI protocol supports for enabling the device either with exclusive permissions for the requesting host or with sharing across the hosts. There are certain devices which are exclusive to Linux context and there are certain devices that are shared across different host contexts. So add support for getting this information from DT by increasing the power-domain cells to 2. For keeping the DT backward compatibility intact, defaulting the device permissions to set the exclusive flag set. In this case the power-domain-cells is 1. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-27firmware: ti_sci: Add a command for releasing all exclusive devicesLokesh Vutla1-0/+75
Any host while requesting for a device can request for its exclusive access. If an exclusive permission is obtained then it is the host's responsibility to release the device before the software entity on the host completes its execution. Else any other host's request for the device will be nacked. So add a command that releases all the exclusive devices that is acquired by the current host. This should be used with utmost care and can be called only at the end of the execution. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-27firmware: ti_sci: Add processor shutdown API methodAndreas Dannenberg2-4/+237
Add and expose a new processor shutdown API that wraps the two TISCI messages involved in initiating a core shutdown. The API will first queue a message to have the DMSC wait for a certain processor boot status to happen followed by a message to trigger the actual shutdown- with both messages being sent without waiting or requesting for a response. Note that the processor shutdown API call will need to be followed up by user software placing the respective core into either WFE or WFI mode. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-07-27firmware: ti_sci: Allow for device shared and exclusive requestsLokesh Vutla1-5/+20
Sysfw provides an option for requesting exclusive access for a device using the flags MSG_FLAG_DEVICE_EXCLUSIVE. If this flag is not used, the device is meant to be shared across hosts. Once a device is requested from a host with this flag set, any request to this device from a different host will be nacked by sysfw. Current tisci driver enables this flag for every device requests. But this may not be true for all the devices. So provide a separate commands in driver for exclusive and shared device requests. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-netTom Rini11-346/+1897
- DaVinci emac DM work - NXP driver work - macb updates for RISC-V
2019-07-25net: sun8i_emac: Test the correct phyEmmanuel Vadot1-8/+21
H3/H5 can either use the internal phy or an external one. Before getting clock and resets for the internal phy, test that we are using it because otherwise it break emac when using an external phy. Tested-on: OrangePi PC2 (H5) Fixes: 2348453c41 (net: sun8i_emac: Add EPHY CLK and RESET support) Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: davinci_emac: convert to using the driver modelBartosz Golaszewski1-35/+42
Now that we removed all legacy boards selecting TI_EMAC we can completely convert the driver code to using the driver model. This patch also updates all remaining users of davinci_emac. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Adam Ford <aford173@gmail.com> #am3517-evm & da850-evm Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2019-07-25net: macb: Fix check for little-endian system in gmac_configure_dma()Anup Patel1-4/+7
Instead of depending on CONFIG_SYS_LITTLE_ENDIAN, we check at runtime whether underlying system is little-endian or big-endian. This way we are not dependent on any U-Boot specific OR compiler specific macro to check system endianness. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: macb: Extend MACB driver for SiFive Unleashed boardAnup Patel1-17/+56
The SiFive MACB ethernet has a custom TX_CLK_SEL register to select different TX clock for 1000mbps vs 10/100mbps. This patch adds SiFive MACB compatible string and extends the MACB ethernet driver to change TX clock using TX_CLK_SEL register for SiFive MACB. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: tsec: Change compatible strings to match LinuxVladimir Oltean1-1/+1
In the case of the tsec network driver, so far there has been no mainline user of DM_ETH where the DT bindings get used. In the case of the mdio bus, it looks like the "fsl,tsec-mdio" string was made up for the documentation, but there is no mainline code that parses the "compatible" property anyway. In both cases, there are no DT blobs that contain the old strings. So change the documentation to "fsl,etsec2" for the Ethernet ports and "fsl,etsec2-mdio" for the MDIO buses, which are strings that Linux also uses, at least for LS1021A. More compatible strings can be added once other (PowerPC) SoCs are migrated to DM_ETH. The current ls1021a.dtsi doesn't match what was documented for the MDIO buses anyway (the "compatible" is "gianfar" currently). This will be fixed in the next patch. Fixes: 69a00875e3db ("doc: dt-bindings: Describe Freescale TSEC ethernet controller") Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: tsec: Common handling of MAC station address for DM_ETHVladimir Oltean1-9/+2
In tsec_init, the MAC address is retrieved from 2 different structures depending on whether DM_ETH is enabled or not. But since the field name is the same inside both structures, we can conditionally define the structure of the correct type and simplify the assignments. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25net: tsec: Make errors visibleVladimir Oltean1-4/+4
This replaces debug() calls with printf() so that it is immediately obvious from the console that something is wrong. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25net: tsec: Reverse Christmas tree notationVladimir Oltean1-5/+5
This is a cosmetic patch that reorders variable definitions in the inverse order of their line length, where possible. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25net: tsec: Fix offset of MDIO registers for DM_ETHVladimir Oltean1-6/+7
By convention, the eTSEC MDIO controller nodes are defined in DT at 0x2d24000 and 0x2d50000, but actually U-Boot does not touch the interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM, MDIO_EMAPM). That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM, MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at the 0x520 offset. So shift the DT-defined register map by the offset of MDIO_MIIMCFG when mapping the MDIO bus registers. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25net: tsec: Refactor the readout of the tbi-handle propertyVladimir Oltean1-8/+7
The point of this patch is to eliminate the use of the locally-defined "reg" variable (which interferes with next patch) and simplify the fallback to the default CONFIG_SYS_TBIPA_VALUE in case "tbi-handle" is missing. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25net/macb: increase RX buffer size for GEMRamon Fried1-8/+23
Macb Ethernet controller requires a RX buffer of 128 bytes. It is highly sub-optimal for Gigabit-capable GEM that is able to use a bigger DMA buffer. Change this constant and associated macros with data stored in the private structure. RX DMA buffer size has to be multiple of 64 bytes as indicated in DMA Configuration Register specification. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: macb: apply sane DMA configurationRamon Fried1-0/+28
DMA configuration was heavily dependent on the HW defaults, add function to properly set the required fields, including the new dma_burst_length. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: macb: add dma_burst_length configRamon Fried1-1/+21
GEM support higher DMA burst writes/reads than the default (4). add configuration structure with dma burst length so it could be applied later to DMA configuration. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: macb: add support for SGMII phy interfaceRamon Fried1-0/+7
This patch adds support for the sgmii phy interface, available only to DM users, dictated by current driver design. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: macb: use bit access macro from header fileRamon Fried1-33/+15
macb.h provides macros for reading/setting bitfields, in macb registers and descriptors. use that instead of redefining them in the source file. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: macb: add support for faster clk ratesRamon Fried2-1/+7
add support for clock rates higher than 2.4Mhz Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: macb: sync header definitions as taken from LinuxRamon Fried2-214/+662
Few registers and bits were added by Cadence and they were not updated in the headers. Take the latest definitions as defined in Linux header (5.1) that also includes some comments about existing registers. One register was improperly named (UR), fix that. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: driver for MDIO muxes controlled over I2CAlex Marginean2-0/+9
This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25net: designware: use 'phy_connect' instead of open codedSimon Goldschmidt1-5/+3
Using 'phy_connect' instead of 'phy_find_by_mask' and 'phy_connect_dev' both deduplicates code and adds support for 'fixed-link'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: fsl_enetc: add support for SGMII 2500Alex Marginean2-7/+23
SGMII 2500 as supported on NXP SoCs requires AN to be disabled, handle this case in the enetc sgmii init code. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: apply serdes configuration for ENETC Ethernet interfacesAlex Marginean3-5/+189
Ethernet interfaces using serial protocols go through the serdes block integrated in the SoC. This is accessed over dedicated internal MDIOs which are part of the Ethernet PCI functions. Set up serdes at _start, along with other protocol specific port/MAC configuration. MDIO code is shared with enetc_mdio, read/write functions are exported from fsl_enetc_mdio for this reason. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: add NXP ENETC MDIO driverAlex Marginean5-2/+229
Adds a driver for the MDIO interface currently integrated in LS1028A SoC. This MDIO interface is shared by multiple ethernet interfaces and is presented as a stand-alone PCI function on the SoC ECAM. Ethernet has a functional dependency on MDIO, for simplicity there is a single config option for both. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: add NXP ENETC ethernet driverAlex Marginean4-0/+556
Adds a driver for NXP ENETC ethernet controller currently integrated in LS1028A. ENETC is a fairly straight-forward BD ring device and interfaces are presented as PCI EPs on the SoC ECAM. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-24dm: device: make power domain calls optionalAnatolij Gustschin1-1/+2
Reduce power domain calls when CONFIG_POWER_DOMAIN is disabled. With gcc v8.2, this change saves 104 bytes. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-24clk: initialize clk->data when using default xlateSekhar Nori1-0/+2
Right now when using clk_of_xlate_default(), clk->data remains un-initialized because clk_get_bulk() does not initialize memory on allocation of clock structure. This can cause problems when data is used to match if two clocks pointers are exactly the same underlying clocks, for example. Fix it by initializing clk->data to 0. Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-07-24dm: core: Set correct "status" value for a nodeBin Meng1-1/+1
Per device tree spec, "status" property can have a value of "okay", or "disabled", but not "disable". Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-24dm: core: Call clk_set_defaults() during probe() only for a valid ofnodeBin Meng1-4/+10
Without a valid ofnode, it's meaningless to call clk_set_defaults() to process various properties. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-24dm: timer: Skip device that does not have a valid ofnode in pre_probe()Bin Meng1-0/+4
It is possible that a timer device has a null ofnode, hence there is no need to further parse DT for the clock rate. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-23Merge tag 'u-boot-stm32-20190723' of ↵Tom Rini13-2/+750
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - add rtc driver for stm32mp1 - add remoteproc driver for stm32mp1 - use kernel qspi compatible string for stm32
2019-07-23Merge tag 'rockchip-for-v2019.07-2' of ↵Tom Rini1-4/+4
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3399 sdhci driver fixup - TPL BANNER fixup
2019-07-22rtc: Add rtc driver for stm32mp1Patrick Delaunay3-0/+330
Add support of STM32MP1 rtc driver. Enable it for basic and trusted configurations. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
2019-07-22clk: stm32mp1: Add RTC clock entryPatrick Delaunay1-0/+9
Add RTCAPB and RTC clock support. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-22spi: stm32_qspi: Remove "st, stm32-qspi" compatible stringPatrice Chotard1-1/+0
"st,stm32-qspi" is no more used, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-07-22remoteproc: Introduce STM32 Cortex-M4 remoteproc driverFabien Dessenne3-0/+268
This patch introduces support of Cortex-M4 remote processor for STM32 MCU and MPU families. Signed-off-by: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-07-22remoteproc: add elf file load supportFabien Dessenne3-1/+126
The current implementation supports only binary file load. Add helpers to support ELF32 format (sanity check, and load). Note that since an ELF32 image is built for the remote processor, the load function uses the device_to_virt ops to translate the addresses. Implement a basic translation for sandbox_testproc. Add related tests. Test result: => ut dm remoteproc_elf Test: dm_test_remoteproc_elf: remoteproc.c Test: dm_test_remoteproc_elf: remoteproc.c (flat tree) Failures: 0 Signed-off-by: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-22dm: core: Introduce xxx_translate_dma_address()Fabien Dessenne3-0/+17
Add the following functions to translate DMA address to CPU address: - dev_translate_dma_address() - ofnode_translate_dma_address() - of_translate_dma_address() - fdt_translate_dma_address() These functions work the same way as xxx_translate_address(), with the difference that the translation relies on the "dma-ranges" property instead of the "ranges" property. Add related test. Test report: => ut dm fdt_translation Test: dm_test_fdt_translation: test-fdt.c Test: dm_test_fdt_translation: test-fdt.c (flat tree) Failures: 0 Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-07-21Merge tag 'rockchip-for-v2019.07' of ↵Tom Rini14-390/+5285
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3399 lpddr4 support - rk3399-rock960 board support improvement - Eliminate pyelftools dependency by make_fit_atf.py - clean up rockchip dts to use -u-boot.dtsi - use ARM arch/generic timer instead of rk_timer - clean up Kconfig options for board support
2019-07-20rockchip: sdhci: Fix sdhci mmc driver probe abortKever Yang1-4/+4
This patch fix mmc driver abort caused by below patch: 3d296365e4 mmc: sdhci: Add support for sdhci-caps-mask After the patch sdhci_setup_cfg() access to host->mmc->dev, so we have to do init before make the call to the function() Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: video: rk3288_hdmi: Add missing call to dw_hdmi_enable()Niklas Schulze1-1/+1
The RK3288 HDMI driver's rk3288_hdmi_enable() currently lacks a call to dw_hdmi_enable(). Thus, the HDMI output never gets enabled. Signed-off-by: Niklas Schulze <me@jns.io> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-07-20rockchip: rk322x: sdram: use udelay instead of rockchip_udelayKever Yang1-15/+14
Use system api for udelay instead of vendor defined api, and rockchip_udelay() will be removed. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add lpddr4 set rate supportJagan Teki1-12/+661
Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. The lpddr4 set rate sequnce will follow by setting lpddr4 - dq out - ca odt - MR3 - MR12 - MR14 registers sets in sequential order. Here is sameple log about LPDDR4-100 init sequence in Rockpro64: Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride channel 0 training pass channel 1 training pass change freq to 400 MHz 0, 1 channel 0 training pass channel 1 training pass change freq to 800 MHz 1, 0 This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add set_rate sdram rk3399 opsJagan Teki1-3/+8
DDR set rate can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops with .set_rate and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add LPPDDR4-800 timings incJagan Teki1-0/+1570
LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-800 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add LPPDDR4-400 timings incJagan Teki1-0/+1570
LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-400 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
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