summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2023-09-07drivers: fastboot: Fix the error of writing sparse file with fastbootXingyu Wu2-0/+7
Add config for max block size to write in MMC with sparse file. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-09-07drivers: fastboot: Add logical-block-size in getvar commandXingyu Wu1-0/+18
Add a new parameter to get "logical-block-size" in getvar command. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-09-07driver: fastboot: Add new flag to load image file without partitionXingyu Wu1-0/+47
Add new flag to load image file to preset address without partition. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-08-31usb: cdns: Add USB device supportMinda Chen2-2/+61
Add USB device support. Add dr_num_mode for changing the dr mode number, For changing the strings cause issues. For devkits, If using device, need to changed starfive,usb2-only to 1 and dr_num_mode to 2. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-30Merge branch 'CR_7199_add_usb_host_minda' into 'jh7110-master'andy.hu1-9/+223
CR_7199 usb: cdns3: starfive: Add usb driver to support for JH7110 See merge request sdk/u-boot!66
2023-08-25usb: cdns3: starfive: Add usb driver to support for JH7110Yanhong Wang1-9/+223
Add usb driver to support for jh7110. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-23usb: cdns3: Set the SS EP config bit by usb SS speedMinda Chen1-4/+6
Set SS EP config bit by USB SS speed. Avoid transfer timeout. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-07-26Merge branch 'CR_6570_SDBOOT_u-boot_william.qiu' into 'jh7110-master'andy.hu1-1/+78
CR_6570: mmc: starfive: add HS200 support See merge request sdk/u-boot!62
2023-07-26mmc: starfive: fix mmc device power-up sequenceWilliam Qiu1-0/+18
fix mmc device power-up sequence. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-07-26mmc: starfive: add HS200 supportWilliam Qiu1-1/+60
Add tuning and other related code to the driver to support HS200 mode. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-07-26pci: Getw correct config addr to support multi PCIMinda Chen1-8/+8
subtract the root bus number to get the correct config addr. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-07-20board: starfive: evb: use dram_init in splSamin Guo1-2/+0
dram_init call fdtdec_setup_mem_size_base, so starfive_ddr.c do not need it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-20Merge branch 'CR_6604_1G_DDR_SYNC_samin.guo' into 'jh7110-master'andy.hu6-68/+2706
CR6604：dram: jh7110: sync from devkits/vf2 See merge request sdk/u-boot!59
2023-07-19dram: starfive: jh7110: Add ddr4 supportSamin Guo6-68/+2706
Add ddr4 tuning support (sync from devkits) Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-18uboot: hdmi logo causes kernel hdmi unstableKeith Zhao4-8/+172
The hdmi display is unstable after repeated reset blank panel or write panel Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-07-10dram: starfive: jh7110: Add 1G supportSamin Guo4-29/+46
add 1G DDR tuning cfg Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-05-10Merge branch 'CR_5042_gmac_phy_delay_ds_samin.guo' into 'jh7110-master'andy.hu1-2/+20
CR5042： net: phy: motorcomm: add Pad Drive Strength Cfg See merge request sdk/u-boot!52
2023-04-23board: starfive: copyright: Standardize the copyright formatYanhong Wang13-14/+13
Unify the content format of the copyright section Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-04-20net: phy: motorcomm: add Pad Drive Strength CfgSamin Guo1-2/+20
YT8531 supports Pad Drive Strength configuration. Including rx_data/rx_clk, etc. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-04cache: sifive: Configure the l2 prefetcher parameterSamin Guo1-0/+93
The default configuration of the SIFIVE L2 Prefetcher may not be the best combination on the JH7110, and some parameters need to be modified to achieve the best performance. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-03-28pinctrl: starfive: Add .get_function ops for the gpio driverHal Feng1-0/+16
Support getting direction of gpio. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-28pinctrl: starfive: Fix the crash problem when using gpio cmdHal Feng1-2/+2
starfive_pinctrl_priv struct is a priv of the parent device (pinctrl device), not the gpio device. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-08hdmi: add hdmi driver in ubootkeith.zhao5-117/+690
hdmi can show a bitmap logo while uboot start and the default resolution is 1920x1080@60fps Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
2023-02-22i2c: designware_i2c: Add ACPI configure limitationMason Huo1-0/+2
As the i2c_designware_pci.c uses ACPI APIs, add the ACPI table generation configuration for its compilation. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22net: rtl8169: Add one more device IDMason Huo1-0/+3
Add the NIC device ID and adjust the bar regions. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22clk: starfive: Add PCIe clocks for PCIe controllerMason Huo1-0/+43
Add the stg clocks for PCIe controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22pci: Add Starfive JH7110 pcie driverMason Huo3-0/+520
Port the JH7110 pcie host driver from linux kernel. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-17vout:dc8200: add vout mipi driverkeith.zhao17-2/+3479
add vout mipi pipeline driver in uboot Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17i2c:desigware-snps: add i2c clock configkeith.zhao3-5/+28
add clock config for i2c2 and i2c5 update the i2c driver clock config Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17power: add power subsystem driver in ubootkeith.zhao9-0/+459
add power subsystem in driver,include pmu pmic and regulator pmu : dc8200 power pmic : mipi power regulator : entend power Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-02sysreset: provide SBI based sysreset driverHeinrich Schuchardt3-0/+64
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-01-06Merge branch 'CR_3006_OTP_yanhong.wang' into 'jh7110-master'andy.hu1-3/+12
CR_3006 misc: OTP: Starfive-jh7110: update the return value of starfive_otp_read See merge request sdk/u-boot!21
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang1-198/+433
Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-03misc: OTP: Starfive-jh7110: update the return value of starfive_otp_readYanhong Wang1-3/+12
Update the return value to match the function prototype definition. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2022-11-21pinctrl: starfive: Add StarFive JH7110 driverKuan Lim Lee8-0/+1028
Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-01net:phy:motorcomm: Support modifying RGMII_TX_CLK delay train from dtsSamin Guo1-173/+269
support use original or inverted RGMII_TX_CLK delay train. 10M/100M/1000M can be configured independently. tx_inverted_xx = val; For example: &gmac0 { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { tx_inverted_10 = <0>; tx_inverted_100 = <1>; tx_inverted_1000 = <1>; }; }; 0: original (default) 1: inverted Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-10-18ram: starfive: Make DDR driver support 8G sizeYan Hong Wang4-733/+547
This patch include four items: 1.rename the driver compatible name. 2.reset action with the common API. 3.clean up code to make it is closer to readable. 4.add configuration to support 8G size Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18ram: starfive: jh7110: Replace the configuration operation for pll1 clkYan Hong Wang2-27/+6
Replace the configuration operation for pll1 clk with common api provide by pll module. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18clk: starfive: jh7110: Modify the parameters of clk_register()Yan Hong Wang1-34/+11
Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18clk:jh7110: update apb_bus clk relationshipyanhong.wang1-26/+7
The previous definition of apb_bus clock relationship is incorrect,so update it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: Make ddr driver support 2G sizeyanhong.wang4-25/+250
The ddr driver include two configs with 2G and 4G.Fist read the ddr size config from the memory node in the dts,then match the right config and do it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive:jh7110: Delete redundant logicyanhong.wang1-28/+1
In the hardware design, the IPs RESET signal of jh7110 is divided into two groups,one group is active high, and the other group is active low. However, the software does not need to distinguish whether the RESET signal is active high or active low,Write 1 to be assert, and write 0 to deassert. Therefore, the software does not need to add additional logic to distinguish these two sets of signals. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:jh7110: pll0 dynamically gets the frequencysamin1-5/+35
pll0 dynamically gets the frequency. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18SPL:reset:starfive-jh7110: support reset in SPLyanhong.wang2-1/+9
Update Kconfig to support reset in SPL for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:riscv:starfive: update uart3-uart5 clksyanhong.wang1-16/+24
Update uart3-uart5 clks register info for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18serial: ns16550: support a list of clkyanhong.wang1-0/+12
Add a list of clk enable operation. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-6/+4
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: change tx delay configyanhong.wang1-1/+1
Modify the tx delay configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: add JH7110_GMAC1_GTXC clkyanhong.wang1-0/+4
Add JH7110_GMAC1_GTXC clk for GMAC1 on JH7110 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:dwc_eth_qos:starfive: remove phy-reset-gpio setyanhong.wang1-18/+1
Phy-reset-gpio set is unused in JH7110 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-20 19:47:18 +0300