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2021-04-20sysreset: provide type of reset in do_reset cmdIgor Opaniuk1-1/+10
Add additional param for reset cmd, which provides type of reset. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20sysreset: psci: use psci driver exported functionsIgor Opaniuk1-6/+2
Use psci driver exported functions for reset/poweroff, instead of invoking directly invoke_psci_fn. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20psci: add features/reset2 supportIgor Opaniuk1-0/+68
Adds support for: * PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API that allows discovering whether a specific PSCI function is implemented and its features. * SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing SYSTEM_RESET. It provides support for vendor-specific resets, providing reset_type as an additional param. For additional details visit [1]. Implementations of some functions were borrowed from Linux PSCI driver code [2]. [1] https://developer.arm.com/documentation/den0022/latest/ [2] drivers/firmware/psci/psci.c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20net: calxedagmac: Convert to DM_ETHAndre Przywara2-64/+135
To squash that nasty warning message and make better use of the newly gained OF_CONTROL feature, let's convert the calxedagmac driver to the "new" driver model. The conversion is pretty straight forward, mostly just adjusting the use of the involved data structures. The only actual change is the required split of the receive routine into a receive and free_pkt part. Also this allows us to get rid of the hardcoded platform information and explicit init calls. This also uses the opportunity to wrap the code decoding the MMIO register base address, to make it safe for using PHYS_64BIT later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-20power: regulator: add driver for ANATOP regulatorYing-Chun Liu (PaulLiu)3-0/+289
Anatop is an integrated regulator inside i.MX6 SoC. There are 3 digital regulators which controls PU, CORE (ARM), and SOC. And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB). This patch adds the Anatop regulator driver. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-20net: octeontx: smi: fix mii probeTim Harvey1-0/+2
The fdt node offset is apparently not set properly when probed causing no MDIO busses to be found. Fix this by obtaining the offset. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-20drivers: ata: ahci: update max id if it is more than available portsSuneel Garapati1-0/+3
After check for maximum between max id and available ports, also check if available port count is less than max id and update. In the case of the CN8030 OcteonTX SoC max_id needs to be reduced to the number of ports found otherwise the following occurs on a scan: GW6404-B> scsi scan scanning bus for devices... Target spinup took 0 ms. AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc apst Device 0: (0:0) Vendor: ATA Prod.: SanDisk SD8SFAT0 Rev: Z233 Type: Hard Disk Capacity: 61057.3 MB = 59.6 GB (125045424 x 512) "Synchronous Abort" handler, esr 0x96000006 elr: 000000000052f824 lr : 000000000052fa10 (reloc) elr: 000000007fee9824 lr : 000000007fee9a10 x0 : 0000000000000001 x1 : 0000000000000001 x2 : 000000007bea3528 x3 : 000000007bea3580 x4 : 0000000000000200 x5 : 0000000000000000 x6 : 0000000000000002 x7 : 000000007bea3540 x8 : 00000000fffffff8 x9 : 0000000000000008 x10: 00000000000186a0 x11: 000000000000000d x12: 0000000000000006 x13: 000000000001869f x14: 0000000000000007 x15: 00000000ffffffff x16: 000000007ff439a5 x17: 000000007ff5730c x18: 000000007bea9de0 x19: 000000007ff7a580 x20: 000000007bec79f8 x21: 0000000000000000 x22: 000000007bea3580 x23: 0000000000000000 x24: 0000000000000000 x25: 000000007bec7a00 x26: 00000000ffffffc0 x27: 000000007bec79d0 x28: 000000007beb51c0 x29: 000000007bea3480 Code: 91246800 940130c2 12800000 1400004f (b9402ae0) Resetting CPU ... Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-20drivers: net: octeontx: fix QSGMIITim Harvey1-13/+7
Revert a change that occured between the Marvell SDK-10.1.1.0 and SDK-10.3.1.1 which broke QSMII phy support. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-20Fix IDE commands issued, fix endian issues, fix non MMIOReinoud Zandijk1-109/+43
Fixes IDE issues found on the Malta board under Qemu: 1) DMA implied commands were sent to the controller in stead of the PIO variants. The rest of the code is DMA free and written for PIO operation. 2) direct pointer access was used to read and write the registers instead of the inb/inw/outb/outw functions/macros. Registers don't have to be memory mapped and ATA_CURR_BASE() does not have to return an offset from address zero. 3) Endian isues in ide_ident() and reading/writing data in general. Names were corrupted and sizes misreported. Tested malta_defconfig and maltael_defconfig to work again in Qemu. Signed-off-by: Reinoud Zandijk <reinoud@NetBSD.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-04-20misc: make CONFIG_IRQ selectable for all platformsWasim Khan1-3/+2
UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ selectable for all platforms. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-20phy: meson-g12a-usb3-pcie: add support for PCIe opsNeil Armstrong1-4/+77
Add the PCIe part of the G12A USB3 PCIe Combo PHY driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-20clk: meson-g12a: add PCIe gatesNeil Armstrong1-0/+2
Add missing gates used for PCIe. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19gpio: atmel_pio4: add support for sama7g5 pio4 version with 5 banksEugen Hristev1-0/+22
Add support for sama7g5 pinctrl variant, with 5 banks with a degraded 8 line only 5th bank. Based on Linux Kernel implementation. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-04-18Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini4-176/+285
This is a patchset which makes away with the .bind() controller indexing workaround which was broken since before v2021.04, and then adds PHY support and MX8M support on top of that. Better add it into the release early to get as much testing as possible done, because this really does a lot of changes to the ehci-mx6 driver.
2021-04-18Merge tag 'ti-v2021.07-rc1' of ↵Tom Rini1-60/+414
https://source.denx.de/u-boot/custodians/u-boot-ti - Support for pinmux status command on beaglebone - Updates for MMC speed modes for J721e-evm - Fix MMC booting on omap35_logic_somlv board
2021-04-18usb: ehci-mx6: Add iMX8M supportMarek Vasut1-1/+3
The iMX8M uses nop PHY, select PHY and NOP_PHY automatically. Otherwise, the DM capable driver is now perfectly compatible. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Fix aarch64 build warningsMarek Vasut1-4/+4
Fix cast from pointer to integer of different size by casting the pointer to uintptr_t instead of uint32_t, the former has correct size on both 32bit and 64bit architectures. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Add fsl,imx7d-usb compatible stringMarek Vasut1-0/+1
Add new compatible string, used by some more up-to-date DTs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Set default CONFIG_MXC_USB_PORTSC if not definedMarek Vasut1-0/+5
There is now multiple copies of CONFIG_MXC_USB_PORTSC in configs set to PORT_PTS_UTMI | PORT_PTS_PTW, which is in fact the default register value for MX6, MX7 and MX7ULP. Define the default value of CONFIG_MXC_USB_PORTSC in the driver and use it in case CONFIG_MXC_USB_PORTSC is not defined in config, to reduce the duplication. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Add generic EHCI PHY supportMarek Vasut1-2/+17
In case PHY support is enabled, use the generic EHCI PHY support to start and stop the PHY. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Use portnr from DT in DM caseMarek Vasut1-45/+7
In case the platform uses DM, determine port number, which is used as offset in USBMISC registers, from PHY node DT aliases, just like Linux does. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Pass MISC address to usb_oc_config()Marek Vasut1-11/+8
Instead of passing ad-hoc sequence number to usb_oc_config(), pass in the USB MISC address itself. The USB MISC address comes from DT in DM case, and from the old method using controller index in non-DM case. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Split usb_power_config()Marek Vasut1-51/+92
Split usb_power_config() per SoC and pass in USB PHY, USBNC and ANATOP addresses instead of ad-hoc sequence numbers. This is only applicable on legacy systems which do not implement proper PHY support. Once PHY support is available, parts of this can be removed altogether and moved to the PHY driver, similar to Linux phy-mxs-usb.c . Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Pass PHY address to usb_*_phy*()Marek Vasut1-19/+10
Instead of passing ad-hoc index to USB PHY handling functions and then try and figure out the PHY address, pass in the PHY address itself. For DM case, this address comes easily from DT. For non-DM case, the previous method is still present, however the non-DM case will soon be removed. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Split ehci_mx6_common_init()Marek Vasut1-30/+30
In order to pass component addresses around easily instead of passing ad-hoc sequence numbers, it is necessary to split ehci_mx6_common_init(). Make it so and call the separate functions instead. Since board_ehci_hcd_init() makes no sense in DM case, do not call it in DM case. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Parse USB PHY and MISC offsets from DTMarek Vasut1-0/+55
In case DM and OF controler is enabled, but PHY support is disabled, parse USB PHY and MISC component addresses from DT manually. Those component addresses will be used in subsequent patches to access the ANATOP, PHY and MISC registers matching the controller and thus get rid of the ad-hoc controller sequence number mapping. Fixes: 4de51cc25b5 ("usb: ehci-mx6: Drop assignment of sequence number") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Unify USBNC registersMarek Vasut1-34/+19
Merge USBNC register layout structure into a single one, instead of having three separate structures and a lot of ifdeffery. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Add DM clock supportMarek Vasut1-5/+32
Add support for using DM clock framework to enable and disable all the necessary clock for the USB controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18usb: ehci-mx6: Turn off Vbus on probe failureMarek Vasut1-2/+27
The driver turns on Vbus regulator in probe, but fails to turn it back off in case of probe failure. Add the missing code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18imx: power-domain: Add fsl,imx8mn-gpc compatible stringMarek Vasut1-0/+1
The driver is compatible with iMX8MN, add missing compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18imx: power-domain: Add fsl,imx8mm-gpc compatible stringMarek Vasut1-0/+1
The driver is compatible with iMX8MM, add missing compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18phy: nop-phy: Add standard usb-nop-xceiv compat stringMarek Vasut1-0/+1
The USB no-op PHY uses "usb-nop-xceiv" compatible string. This driver is compatible with USB no-op PHY, so add the compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-16sunxi: video: select dw-hdmi in Kconfig, not MakefileJernej Skrabec1-1/+1
Currently sunxi Makefile manually specifies full path to dw-hdmi common code. However, that is not needed because it can be selected in Kconfig instead. Select proper symbol in Kconfig and drop path from Makefile. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-16clk: sunxi: h6: Add XHCI clocksSamuel Holland1-0/+2
The XHCI controller has its own clock and reset. Add them. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-16clk: sunxi: Add a dummy clock driver for the RTCSamuel Holland2-0/+37
The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is used, among other things, by the XHCI controller in the H6. To be able to call clk_get_bulk() on the XHCI controller, some device needs to provide all referenced clocks. Since LOSC is a fixed-rate always-on clock, implementation is trivial. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-15Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini14-97/+490
update ls1028aqds networking protocol, config in ls1021atwr, env in ls1012a Add seli3 board support, booke watchdog, update eTSEC support in ppc-qemu Add DM_SERIAL and lpuart in sl28, add DM_ETH support for some of powerpc platforms Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15test: dm: Add a test case for simple-bus <ranges>Bin Meng1-0/+1
This adds a test case to verify reading <ranges> of a simple-bus is working as expected. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15dm: core: Correctly read <ranges> of simple-busBin Meng2-7/+38
At present we decode simple bus <ranges> using the following assumption: - parent #address-cells 1 - child #address-cells 1 - child #size-cells 1 However this might not always be the case. Update to use fdt_addr_t and fdt_size_t in 'struct simple_bus_plat', and use fdt_read_ranges() to correctly decode it according to the actual parent and child #address-cells / #size-cells under a Kconfig option CONFIG_SIMPLE_BUS_CORRECT_RANGE which can be turned on for any board that needs it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: tsec: Support <reg> property from the subnode "queue-group"Bin Meng1-3/+27
At present the tsec driver uses a non-standard DT bindings to get its <reg> base / size. The upstream Linux kernel seems to require the <reg> base / size to be put under a subnode of the eTSEC node with a name prefix "queue-group". This is not documented in the kernel DT bindings, but it looks every dtsi file that contains the eTSEC node was written like this. This commit updates the tsec driver to handle this case. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: tsec: Use map_physmem() directly instead of dev_remap_addr()Bin Meng1-1/+3
dev_remap_addr() eventually calls dev_read_addr_index(), while pdata->iobase holds the return value of dev_read_addr() that calls dev_read_addr_index() too. Such duplication can be avoided by using map_physmem() directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15sandbox: Add a DSA sandbox driver and unit testClaudiu Manoil3-0/+189
The DSA sandbox driver is used for unit testing the DSA class code. It implements a simple 2 port switch plus 1 CPU port, and uses a very simple tag to identify the ports. The DSA sandbox device is connected via CPU port to a regular Ethernet sandbox device, called 'dsa-test-eth, managed by the existing eth sandbox driver. The 'dsa-test-eth' is not intended for testing the eth class code however, but it is used to emulate traffic through the 'lan0' and 'lan1' front pannel switch ports. To achieve this the dsa sandbox driver registers a tx handler for the 'dsa-test-eth' device. The switch ports, labeled as 'lan0' and 'lan1', are also registered as eth devices by the dsa class code this time. So pinging through these switch ports is as easy as: => setenv ethact lan0 => ping 1.2.3.5 Unit tests for the dsa class code were also added. The 'dsa_probe' test exercises most API functions from dsa.h. The 'dsa' unit test simply exercises ARP/ICMP traffic through the two switch ports, including tag injection and extraction, with the help of the dsa sandbox driver. I took care to minimize the impact on the existing eth unit tests, though some adjustments needed to be made with the addition of extra eth interfaces used by the dsa unit tests. The additional eth interfaces also require MAC addresses, these have been added to the sandbox default environment. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-Id: <20210216224804.3355044-5-olteanv@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: tsec: Use dm_eth_phy_connect() directly for the DM caseVladimir Oltean1-5/+1
Now that the fixed phy driver has been fully adapted to OF APIs, and dm_eth_phy_connect() already can handle the fixed phy, call dm_eth_phy_connect() directly in the DM tsec driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210216224804.3355044-4-olteanv@gmail.com> [bmeng: split from "net: mdio: teach dm_eth_phy_connect to connect to fixed PHY"] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: phy: fixed: Support the old DT bindingBin Meng1-3/+23
Update fixedphy_probe() to support the old DT binding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: phy: fixed: Add the missing ending newlineBin Meng1-1/+1
The printf statement doesn't end with a newline. Add it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: phy: fixed: Make driver ops staticBin Meng1-4/+4
The PHY driver ops should be made static. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: phy: Simplify the logic of phy_connect_fixed()Bin Meng1-8/+8
Simplify the logic of phy_connect_fixed() by using the new API ofnode_phy_is_fixed_link(), which brings additional bonus of supporting the old DT bindings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: phy: xilinx: Drop #ifdef CONFIG_DM_ETH around phy_connect_gmii2rgmii()Bin Meng2-6/+1
At present phy_connect_gmii2rgmii() is implemented using a DM API dev_of_offset() hence it cannot support a non-DM configuration. Remove the non-DM version prototype of phy_connect_gmii2rgmii() and make the driver depend on CONFIG_DM_ETH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: phy: xilinx: Be compatible with live OF treeBin Meng2-44/+40
Following the same updates that were done to the fixed phy driver, use ofnode_ APIs instead of fdt_ APIs so that the Xilinx PHY driver can support live DT. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: phy: fixed: Drop #ifdef CONFIG_DM_ETH around phy_connect_fixedVladimir Oltean1-6/+0
In drivers/net/phy/Kconfig, CONFIG_PHY_FIXED already depends on CONFIG_DM_ETH, so the function prototype definition when CONFIG_DM_ETH=n does nothing, so it can be dropped. It is also never reachable, since the whole function is already under #ifdef CONFIG_PHY_FIXED (which again, as I said, depends on CONFIG_DM_ETH=y). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210216224804.3355044-3-olteanv@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-15net: phy: fixed: Be compatible with live OF treeVladimir Oltean2-24/+32
On systems that use CONFIG_OF_LIVE, the "ofnode" type is defined as const struct device_node *np, while on the flat DT systems it is defined as a long of_offset into gd->fdt_blob. It is desirable that the fixed PHY driver uses the higher-level ofnode abstraction instead of parsing gd->fdt_blob directly, because that enables it to work on live OF systems. The fixed PHY driver has used a nasty hack since its introduction in commit db40c1aa1c10 ("drivers/net/phy: add fixed-phy / fixed-link support"), which is to pass the long gd->fdt_blob offset inside int phydev->addr (a value that normally holds the MDIO bus address at which the PHY responds). Even ignoring the fact that the types were already mismatched leading to a potential truncation (flat OF offset was supposed to be a long and not an int), we really cannot extend this hack any longer, because there's no way an int will hold the other representation of ofnode, the struct device_node *np. So we unfortunately need to do the right thing, which is to use the framework introduced by Grygorii Strashko in commit eef0b8a930d1 ("net: phy: add ofnode node to struct phy_device"). This will populate phydev->node for the fixed PHY. Note that phydev->node will not be valid in the probe function, since that is called synchronously from phy_device_create and we really have no way of passing the ofnode directly through the phy_device_create API. So we do what other drivers do too: we move the OF parsing logic from the .probe to the .config method of the PHY driver. The new function will be called at phy_config() time. I do believe I've converted all the possible call paths for creating a PHY with PHY_FIXED_ID, so there is really no reason to maintain compatibility with the old logic of retrieving a flat OF tree offset from phydev->addr. We just pass 0 to phydev->addr now. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210216224804.3355044-2-olteanv@gmail.com> [bmeng: keep fixedphy_probe(); update mdio-uclass.c to handle fixed phy] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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