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2020-01-16Merge tag 'mmc-1-16-2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini4-70/+39
- Cleanup of fsl_esdhc driver together with arch/defconfig change - Add quirk for APP_CMD retry
2020-01-16Merge tag 'xilinx-for-v2020.04' of ↵Tom Rini6-220/+314
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.04 ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default
2020-01-16mmc: add mmc and sd support for MT7622Sam Shih1-0/+10
This patch add mmc and sd support for Mediatek MT7622 SoCs Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16power: domain: add power domain support for MT7622Sam Shih1-0/+6
This patch add power domain support for Mediatek MT7622 SoCs Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16clk: mediatek: fix clock-rate overflow problemSam Shih1-3/+3
This patch fix clock-rate overflow problem in mediatek clock driver common part. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: add driver for MT7622Sam Shih2-0/+679
This patch add clock driver for MediaTek MT7622 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16pinctrl: mediatek: add support for different pinctrlSam Shih7-19/+125
Due to the pinctrl hardware of MT7622 is difference from others SoC which using the common part of mediatek pinctrl. So we need to modify the common part of mediatek pinctrl. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16pinctrl: mediatek: add driver for MT7622Sam Shih3-0/+757
This patch add Pinctrl driver for MediaTek MT7622 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16phy: phy-mtk-tphy: make ref clock optionalChunfeng Yun1-1/+2
If make the ref clock optional, no need refer to fixed-clock when the ref clock is always on or comes from oscillator directly. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16phy: phy-mtk-tphy: remove the check of -ENOSYSChunfeng Yun1-2/+1
No need check -ENOSYS anymore after add dummy_enable() for fixed-clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: fixed_rate: add dummy enable() functionChunfeng Yun1-0/+7
This is used to avoid clk_enable() return -ENOSYS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: add APIs to get (optional) clock by name without a deviceChunfeng Yun1-0/+28
Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: check valid clock by clk_valid()Chunfeng Yun1-8/+8
Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: fix error check for devm_clk_get_optional()Chunfeng Yun1-1/+1
If skip all return error number, it may skip some real error cases, so only skip the error when the clock is not provided in DTS Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: mt7629: add support for ssusbsysChunfeng Yun1-0/+42
The SSUSB IP's clocks come from ssusbsys module on mt7629, so add its driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16mmc: mtk-sd: fix hang when data read quicklymingming lee1-5/+1
For CMD21 tuning data, the 128/64 bytes data may coming in very short time, before msdc_start_data(), the read data has already come, in this case, clear MSDC_INT will cause the interrupt disappear and lead to the thread hang. the solution is just clear all interrupts before command was sent. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCsmingming lee1-33/+101
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs. MT8512/MT8110 SoCs puts the tune register at top layer, so need add new code to support it. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16pinctrl: mediatek: add driver for MT8512mingming lee3-0/+392
Add Pinctrl driver for MediaTek MT8512 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pllmingming lee2-8/+20
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
2020-01-16clk: mediatek: add set_clr_upd mux type flowmingming lee2-11/+55
Add new set_clr_upd mux type and related operation to mtk common clock driver to support mt8512
2020-01-16clk: mediatek: add driver support for MT8512mingming lee2-0/+874
Add clock driver for MediaTek MT8512 SoC, include topckgen, apmixedsys and infracfg support. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16mmc: config help typo fixJoel Johnson1-1/+1
Fix typo in description of MMC_QUIRKS config option. Signed-off-by: Joel Johnson <mrjoel@lixil.net>
2020-01-16mmc: add additional quirk for APP_CMD retryJoel Johnson1-1/+16
It was observed (on ClearFog Base) that sending MMC APP_CMD returned an error on the first attempt. The issue appears to be timing related since even inserting a puts() short debug entry before the execution added sufficient delay to receive success on first attempt. Follow the existing quirks pattern to retry if initial issuance failed so as to not introduce any delay unless needed. Signed-off-by: Joel Johnson <mrjoel@lixil.net>
2020-01-16Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usageYangbo Lu2-19/+22
The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16mmc: fsl_esdhc: drop useless fdt fixupYangbo Lu1-9/+0
The fdt fixup for properties "peripheral-frequency" and "adapter-type" was once for a Freescale SDK release. The properties haven't been existed in linux mainline. Drop these useless code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16mmc: fsl_esdhc_imx: drop QorIQ eSDHC specific peripheral clock codeYangbo Lu1-40/+0
Drop QorIQ eSDHC specific peripheral clock code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16Add dependencies for MALLOC_F and OF_LIBFDTSean Anderson1-0/+3
Some features implicitly depended on MALLOC_F and OF_LIBFDT and would fail at link-time if these features were not enabled. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-01-16Kconfig: Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMAVignesh Raghavendra1-1/+1
Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use macros such as CONFIG_IS_ENABLED() that allow conditional compilation of code for SPL and U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-15mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhcGiulio Benetti2-2/+3
Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms with CONFIG_DM_MMC=y. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statementGiulio Benetti1-19/+19
Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK instead. So building could result in failure due to missing mxc_get_clock(). Make if(CONFIG_IS_ENABLED(CLK)) an #if statement. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15ram: add SDRAM driver for i.MXRT SoCsGiulio Benetti3-0/+449
Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15serial_lpuart: add support for i.MXRTGiulio Benetti1-4/+11
Add i.MXRT compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations. Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so this definition should change to 0x08 as done for i.MX8. It needs also to set baudrate the same way as i.MX8 does. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15serial_lpuart: add clock enable if CONFIG_CLK is definedGiulio Benetti1-0/+16
This driver assumes that lpuart clock is already enabled before probing but using DM only lpuart won't be automatically enabled so add clk_enable() when probing if CONFIG_CLK is defined. If clock is not found, because DM is not used, let's emit a warning and proceed, because serial clock could also be already enabled by non DM code. If clock is found but cna't be enabled then return with error. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15gpio: mxc_gpio: add support for i.MXRT1050Giulio Benetti1-3/+4
Add i.MXRT1050 support, there are 5 GPIO banks. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15pinctrl: add i.MXRT driverGiulio Benetti3-0/+55
Add i.MXRT pinctrl driver. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15clk: imx: add i.IMXRT1050 clk driverGiulio Benetti3-0/+310
Add i.MXRT1050 clk driver support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15clk: imx: pfd: add set_rate()Giulio Benetti1-0/+22
Implement set_rate() for pfd. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-15clk: imx: pllv3: add support for PLLV3_AV typeGiulio Benetti1-0/+76
Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15clk: imx: pllv3: add PLLV3_SYS supportGiulio Benetti1-0/+53
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-15clk: imx: pllv3: add set_rate() supportGiulio Benetti1-0/+27
Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-15clk: imx: pllv3: add disable() supportGiulio Benetti1-0/+16
Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-15clk: imx: pllv3: add enable() supportGiulio Benetti1-0/+24
Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-15clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USBGiulio Benetti1-0/+2
div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-15clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocksGiulio Benetti1-5/+15
Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-15clk: imx8qxp: extend to support getting I2C IPG clockAnatolij Gustschin1-0/+12
Since commit d02be21d3004 ("i2c: imx_lpi2c: add ipg clk") getting I2C clocks doesn't work. Add I2C IPG clock IDs to related switch statements to fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-15mmc: fsl_esdhc_imx: Handle the "broken-cd" propertyFabio Estevam1-0/+8
When no GPIO is used to read the card detect status the following error is seen: MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... MMC: no card present *** Warning - No block device, using default environment Fix it by handling the "broken-cd" property in the same way that drivers/mmc/sdhci.c does, which considers that the SD card is present when the "broken-cd" property is passed. Tested on a imx6ul-evk board. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-01-14net: zynq: Add a note about RX_BUF macroMichal Simek1-0/+1
Record note about reducing number of BDs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14firmware: Remove probe which is causing extra bindAshok Reddy Soma1-1/+0
Remove probe function dm_scan_fdt_dev from zynqmp-firmware driver. It is just binding its subnode zynqmp-clk. As a result one extra node is showing up in dm tree. This is not required, it is anyway bound from it's own zynqmp-clk driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14zynq: mtd: nand: Remove hardcoded base addressesAshok Reddy Soma1-37/+57
Remove hardcoded base addresses of smc controller and nand controller. Get those addresses from dt and replace wherever they are used. Remove smc and nand base address from header file too. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14zynq: mtd: nand: Move zynq nand driver to driver modelAshok Reddy Soma2-11/+34
Move the zynq nand driver to driver model. Select DM_MTD if zynq nand controller (NAND_ZYNQ) is selected. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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