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2022-02-09sata: sata_sil: Only support BLKSimon Glass1-115/+3
No boards use this driver without CONFIG_BLK, so clean up the dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Rearrange Kconfig for SATASimon Glass1-34/+37
Move the SATA options inside an 'if SATA' part, so they are grouped. Fix the 'Complient' typo while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Only support BLKSimon Glass2-30/+1
No boards currently use SATA without BLK: ./tools/moveconfig.py -f SATA ~BLK 0 matches Make SATA depend on BLK to avoid any future confusion. Drop the dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Drop Silicon Image SIL3114 SATA driverSimon Glass4-978/+0
This is not used in U-Boot and has not been converted to driver model. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09Convert CONFIG_SYS_IDE_MAXBUS et al to KconfigSimon Glass1-0/+104
This converts the following to Kconfig: CONFIG_SYS_IDE_MAXBUS CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ATA_STRIDE CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_ALT_OFFSET CONFIG_SYS_ATA_IDE0_OFFSET CONFIG_SYS_ATA_IDE1_OFFSET CONFIG_ATAPI CONFIG_IDE_RESET Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09ide: Drop CONFIG_IDE_AHBSimon Glass1-22/+0
This is not used in U-Boot anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09mmc: fsl: Use brackets around if()Simon Glass1-1/+1
At present the IS_ENABLED() macro has extra brackets, making it possible to write: if IS_ENABLED(CONFIG_XXX) but it is a bit confusing. Add the missing brackets. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-08phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju1-16/+42
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade1-1/+377
Add register sequences for PCIe + QSGMII PHY multilink configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade1-8/+145
Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade1-3/+215
Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade1-1/+40
PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-0/+35
Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade1-0/+38
Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ↵Swapnil Jakhade1-6/+6
documentation No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add support to get SSC type from device tree.Swapnil Jakhade1-1/+5
Add support to get SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade1-53/+135
Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCEAswath Govindraju1-1/+1
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clockAswath Govindraju1-13/+210
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's possible to select one of these two inputs from device tree. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add a UCLASS_PHY device for linksAswath Govindraju1-41/+75
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes instance. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I1-0/+2
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I1-10/+15
Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I1-0/+19
No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I1-22/+35
No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I1-0/+4
Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I1-1/+6
Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: sierra: Fix for USB3 U1/U2 stateSanket Parmar1-13/+14
Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by: Sanket Parmar <sparmar@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08remoteproc: ipu: Add driver to bring up ipuKeerthy3-0/+770
The driver enables IPU support. Basically enables the clocks, timers, watchdog timers and bare minimal MMU and supports loading the firmware from mmc. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: fix compile warnings] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08remoteproc: uclass: Add remoteproc resource handling helpersKeerthy1-0/+534
Add remoteproc resource handling helpers. These functions are primarily to parse the resource table and to handle different types of resources. Carveout, devmem, trace & vring resources are handled. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: fix redefinition of "struct resource_table" and compile warnings ] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08drivers: misc: Makefile: Enable fs_loader compilation at SPL LevelKeerthy2-1/+10
Enable fs_loader compilation at SPL Level. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: fix compilation failures for J721e platform] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08reset: dra7: Add a reset driverKeerthy3-0/+104
Add a reset driver to bring IPs out of reset. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: reset_ops structure member "free" has been renamed to "rfree", use the latter instead] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08soc: soc_ti_k3: update j721e revision numberingBryan Brattlof1-13/+27
There is a 4 bit VARIANT number inside the JTAGID register that TI increments any time a new variant for a chip is produced. Each family of TI's SoCs uses a different versioning scheme based off that VARIANT number. CC: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-02-08soc: ti: k3-socinfo: Add entry for J721S2 SoCDavid Huang1-0/+4
Add support for J721S2 SoC identification. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08ram: k3-ddrss: Add support for J721S2 SoCDavid Huang1-1/+1
Add support for DDR subsystem in J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08power: domain: ti: Add support for J721S2 SoCDavid Huang1-0/+5
Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-08clk: clk-k3: Add support for J721S2 SoCDavid Huang1-0/+5
Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08drivers: dma: Add support for J721S2David Huang5-3/+208
Add support for DMA in J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08ram: k3-ddrss: Add support for configuring MSMC subsystem in case of ↵Aswath Govindraju1-0/+158
Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08ram: k3-ddrss: Add support for multiple instances of DDR subsystemsAswath Govindraju1-51/+87
The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instanceAswath Govindraju1-0/+1
Add a pointer to ddr instance int the lpddr4_privatedata_s structure for supporting mutliple instances of DDR in the drivers. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08remoteproc: k3_system_controller: Support optional boot_notification channelNishanth Menon1-1/+19
If there is an optional boot notification channel that an SoC uses separate from the rx path, use the same. Signed-off-by: Nishanth Menon <nm@ti.com>
2022-02-05clk: imx: select [SPL_]CLK_COMPOSITE_CCF for imxrt10{20|50}Heiko Thiery1-0/+4
The clock composite is required when using the clock framework. So select it automatically. Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2022-02-05regulator: bd718x7: Bypass bogus warningsMarek Vasut1-33/+36
When regulator consumer attempts to set enabled DVS regulator voltage, the driver aborts with "Only DVS bucks can be changed when enabled". In case the regulator is already set to specified voltage, do nothing instead of failing outright. When regulator consumer attempts to set enables regulator which cannot be controlled because it is already always enabled, the driver aborts with -EINVAL. Again, do nothing in such case and return 0, because the request is really fulfilled, the regulator is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
2022-02-05GPIO: fxl6408: Add support for FXL6408 GPIO expanderOleksandr Suvorov3-0/+388
Initial support for Fairchild's 8 bit I2C gpio expander FXL6408. The CONFIG_FXL6408_GPIO define enables support for such devices. Based on: https://patchwork.kernel.org/patch/9148419/ Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-02-05spi: mxc_spi: remove redundant code in spi_xchg_single()Haolin Li1-2/+0
The value of cnt is overwritten without being used. Signed-off-by: Haolin Li <li.haolin@qq.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05imx8ulp: ddr: Fix DDR frequency request issueYe Li1-3/+7
After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp:ddr: saving the dram config timing data into sramJacky Bai2-0/+52
On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-03net: ti: am65-cpsw: Cleanup resources before jump to kernelVignesh Raghavendra1-1/+1
In case fastboot over Ethernet, am65_cpsw_stop() is not called unless DM_FLAG_OS_PREPARE is set. Without call to am65_cpsw_stop(), DMA resources are not released thus leading to failures in kernel. Fix this by adding DM_FLAG_OS_PREPARE flag to am65_cpsw_nuss_port driver. Reported-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-02-02Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini4-9/+17
Update and fixes for ls1088a, FMAN, ls1046ardb, ls1043ardb sync ls1028ardb u-boot and Linux device-tree
2022-02-01mtd: cfi_mtd: populate mtd->dev with flash_info->devPatrice Chotard1-0/+3
Populate mtd->dev with flash_info->dev which allows to get full mtd information using the "mtd list" command. Before, "mtd list" command returns : List of MTD devices: * nor0 - type: NOR flash - block size: 0x40000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "nor0" After this patch we get for example: List of MTD devices: * nor0 - device: flash@0 - parent: spi@40430000 - driver: cfi_flash - path: /soc/spi@40430000/flash@0 - type: NOR flash - block size: 0x40000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "nor0" Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Stefan Roese <sr@denx.de>
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