summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2019-06-11spi: imx: work with cs greater 0Heiko Schocher1-22/+52
currently spi mxc driver can only handle cs 0. Allow it to handle also cs > 0. Signed-off-by: Heiko Schocher <hs@denx.de>
2019-06-11spi: imx: remove doubled pointer from mxc_spi_probeHeiko Schocher1-4/+3
in mxc_spi_probe() plat and mxcs pointer are created: struct mxc_spi_slave *plat = bus->platdata; struct mxc_spi_slave *mxcs = dev_get_platdata(bus); which have the same value. Remove plat pointer. Signed-off-by: Heiko Schocher <hs@denx.de>
2019-06-11Revert "drivers/crypto/fsl: assign job-rings to non-TrustZone"Breno Matheus Lima2-11/+0
Commit 22191ac35344 ("drivers/crypto/fsl: assign job-rings to non-TrustZone") breaks HABv4 encrypted boot support in the following i.MX devices: - i.MX6UL - i.MX7S - i.MX7D - i.MX7ULP For preparing a HABv4 encrypted boot image it's necessary to encapsulate the generated DEK in a blob. In devices listed above the blob generation function takes into consideration the Job Ring TrustZone ownership configuration (JROWN_NS) and can be only decapsulated by the same configuration. The ROM code expects DEK blobs encapsulated by the Secure World environments which commonly have JROWN_NS = 0. As U-Boot is running in Secure World we must have JROWN_NS = 0 so the blobs generated by dek_blob tool can be decapsulated by the ROM code. Job-rings assignment is now handled in OP-TEE OS, this commit can be safely reverted. https://github.com/OP-TEE/optee_os/pull/2986 This reverts commit 22191ac353445ad8fafc5a78aefcd94e78963041. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2019-06-11regulator: bd71837: copy the bd71837 pmic driver from NXP imx u-bootMatti Vaittinen3-0/+97
https://source.codeaurora.org/external/imx/uboot-imx cherry picked, styled and merged commits: - MLK-18387 pmic: Add pmic driver for BD71837: e9a3bec2e95a - MLK-18590 pmic: bd71837: Change to use new fdt API: acdc5c297a96 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-06-11power: pfuze100: Fix off by one error in voltage table handlingTrent Piepho1-2/+2
The code that sets a regulator by looking up the voltage in a table had an off by one error. vsel_mask is a bitmask, not the number of table entries, so a vsel_mask value of 0x7 indicates there are 8, not 7, entries in the table. Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com>
2019-06-03Merge tag 'efi-2019-07-rc4' of git://git.denx.de/u-boot-efiTom Rini1-1/+1
Pull request for UEFI sub-system for v2019.07-rc4 Corrections for boottime services for protocols and for the SetTime() service are provided. Error messages for the 'setenv -e' and 'bootefi bootmgr' commands are added.
2019-06-01dm: net: macb: Implement link speed change callbackBin Meng1-0/+35
At present the link speed change callback is a nop. According to macb device tree bindings, an optional "tx_clk" is used to clock the ethernet controller's TX_CLK under different link speed. In 10/100 MII mode, transmit logic must be clocked from a free running clock generated by the external PHY. In gigabit GMII mode, the controller, not the external PHY, must generate the 125 MHz transmit clock towards the PHY. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-06-01dm: net: macb: Update macb_linkspd_cb() signatureBin Meng1-1/+21
This updates DM version macb_linkspd_cb() signature for future expansion, eg: adding an implementation for link speed changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-06-01clk: sifive: Add clock driver for GEMGXL MGMTBin Meng3-0/+69
This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-06-01rtc: export rtc_month_days()Heinrich Schuchardt1-1/+1
Export function rtc_month_days() for reuse in the UEFI subsystem. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-31Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchipTom Rini1-0/+2
- some fix for rk3399-puma; - rockchip script make_fit_atf.py cleanup - Enable TPL for rk3399 orangepi and nanopi4; - add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
2019-05-31clk: meson-g12a: Add PCIE PLL supportNeil Armstrong1-0/+103
The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed for USB to operate, add basic support for it and associated gates. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-05-30rockchip: clk: rk3399: allow requests for all UART clocksChristoph Muellner1-0/+2
This patch adds the rate for UART1 and UART3 the same way as already implemented for UART0 and UART2. This is required for boards, which have their console output on these UARTs. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-29Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini6-0/+518
- Audio support
2019-05-28dm: arm: bcmstb: Enable driver model MMC supportThomas Fitzsimmons1-18/+55
For bcm7445 and bcm7260, this patch enables CONFIG_DM_MMC and updates the bcmstb SDHCI driver to use the new driver model. This allows removal of SDHCI configuration handling from bcmstb.c, and eliminates a board removal compile warning. Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org> Reviewed-by: Stefan Roese <sr@denx.de>
2019-05-27Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini5-13/+596
- Gen3 PCIe driver + enablement on Salvator-X platforms. - Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon. - SDHI HS400 fixes ported from latest BSP and datasheet.
2019-05-27Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini1-3/+2
- SoCFPGA PL310 cleanup + A10 fix, A10 DT cleanup, DW GPIO fix.
2019-05-26configs: Migrate CONFIG_FMAN_ENET and some related options to KconfigTom Rini3-1/+40
Move the main symbol for Freescale Fman Ethernet controller option to Kconfig. Also migrate the CONFIG_SYS_QE_FMAN_FW_IN_xxx macros and rename the SPIFLASH one to follow the same format as all of the others. To do this fully we need to migrate CONFIG_QC, do so. Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-24sound: tegra: Add a sound driverSimon Glass2-1/+101
Add a sound driver for tegra devices. This connects the audio hub, I2S controller and audio codec to allow sound output. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-05-24tegra: sound: Add an I2S driverSimon Glass3-1/+153
Add a driver which supports transmitting digital sound to an audio codec. This uses fixed parameters as a device-tree binding is not currently defined. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-05-24tegra: sound: Add an audio hub driverSimon Glass3-0/+266
Add a driver for the audio hub. This is modelled as a misc device which supports writing audio data from I2S. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-05-24Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-bootTom Rini13-39/+3814
- Add various STM32MP1 fixes for serial, env, clk, board, i2c ... - Add STM32MP1 DDR driver update: These update introduce the DDR interactive mode described in: https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode This mode is used by the CubeMX: DDR tuning tool. https://wiki.st.com/stm32mpu/index.php/STM32CubeMX The DDR interactive mode is NOT activated by default because it increase the SPL size and slow down the boot time (200ms wait added).
2019-05-24Merge git://git.denx.de/u-boot-mpc85xxTom Rini6-2/+1061
- Enable DM for SATA, SDHC, USB in T2080QDS
2019-05-24drivers: serial: mcfuart: add DT supportAngelo Dureghello2-78/+36
This patch adds devicetree support to the mcfuart.c driver and removes non DM code. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2019-05-24drivers: spi: cf_spi: convert to driver modelAngelo Dureghello1-177/+305
Converting to driver model and removes non-dm code. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2019-05-24drivers: spi: cf_spi: add Kconfig optionAngelo Dureghello1-0/+6
This patch adds cf_spi DM Kconfig option. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2019-05-24gpio: dwapb_gpio: fix broken dev->nodeSimon Goldschmidt1-3/+2
commit 1b898ffc040b ("gpio: dwapb_gpio: convert to livetree") introduced a bug in that dev->node of the gpio chip was accidentally set to the of_node of its bank subnode. What it meant to do was assign subdev->node, not dev->node. While this doesn't affect too many use cases, iterating over the gpio chip's properties doesn't work any more after that, so fix this. Fixes: commit 1b898ffc040b ("gpio: dwapb_gpio: convert to livetree") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-23ata: fsl_ahci: Add sata DM support for Freescale powerpc socsPeng Ma4-0/+1042
This patch is to support Freescale sata driver with dts initialized. Also resolved the following problems. ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-23usb: ehci: adopt 32 bit address for CONFIG_PPCYinbo Zhu1-1/+9
adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. So adopt 32 bit address for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-23stm32mp1: ram: add tuning in DDR interactive modePatrick Delaunay6-1/+1414
Add command tuning for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to execute software tuning for the DDR configuration: - software read DQS Gating (replace the built-in one) - Bit de-skew - Eye Training or DQS training Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: add tests in DDR interactive modePatrick Delaunay5-0/+1541
Add command tests for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to verify the DDR configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: add interactive mode for DDR configurationPatrick Delaunay4-0/+713
This debug mode is used by CubeMX DDR tuning tools or manualy for tests during board bring-up. It is simple console used to change DDR parameters and check initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: add support for LPDDR2/LPDDR3Patrick Delaunay2-3/+10
Manage power supply configuration for board using stpmic1 with LPDDR2 or with LPDDR3: + VDD_DDR1 = 1.8V with BUCK3 (bypass if possible) + VDD_DDR2 = 1.2V with BUCK2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: update parameter array initializationPatrick Delaunay2-16/+33
Force alignment of the size of parameters array with the expected value in the binding, that allows compilation error when the array size change. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: change ddr speed to kHzPatrick Delaunay3-11/+11
Allow fractional support in DDR tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: increase the delay after reset to 128 cyclesPatrick Delaunay1-5/+3
Component Notification DDR controller errata (3.00a):9001313030 Synchronization Time Waited After De-assertion of presetn is 128 pclk Cycles. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: update mask for operating modePatrick Delaunay1-1/+1
Regression introduced by rebase, when loop was replaced by readl_poll_timeout() function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23serial: stm32: remove watchog reset in debug putcPatrick Delaunay1-1/+1
For STM32MP, the watchdog is based on DM and the function watchod_reset call the function uclass_get_device(UCLASS_WDT) to found the driver associated IWDG2. As this reset is not mandatory in debug putc (the uart fifo will be empty after some us), we can simplify the code by removing this call. And this patch avoid issue when putc is called before initialization of DM core, before the parsing of the device tree parsing and each node bound to driver; that also avoid memory leak. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23serial: stm32: remove unnecessary tracePatrick Delaunay1-1/+0
Remove the trace indicating the end of the DEBUG initialization Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23clk: stm32mp1: add set_rate for DDRPHYC clockPatrick Delaunay1-0/+83
Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23i2c: stm32f7: improve loopback in timing algorithmNicolas Le Bayon1-0/+4
This avoids useless loops inside the I2C timing algorithm. Actually, we support only one possible solution per prescaler value. So after finding a solution with a prescaler, the algorithm can switch directly to the next prescaler value. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23i2c: stm32f7: Fix SDADEL minimum formulaNicolas Le Bayon1-1/+1
It conforms with Reference Manual I2C timing section. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23driver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPCYinbo Zhu1-1/+4
PowerPC supports 32 bit address. So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-23driver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPCYinbo Zhu1-0/+6
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22Merge tag 'dm-pull-22may19' of git://git.denx.de/u-boot-dmTom Rini4-8/+89
Various DM fixes Addition of ofnode_get_addr_size_index()
2019-05-22driver: watchdog: add sp805 watchdog supportQiang Zhao3-0/+135
sp805 is watchdog on some NXP layerscape SoCs, adding it's driver. Configs CONFIG_WDT_SP805, CONFIG_WDT, CONFIG_CMD_WDT needs to be enabled to use it. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22scsi: ceva: Clean up the driver codePeng Ma1-17/+33
Distinguish the ecc val by chassis version and move the ecc addr to dts. Add ls1028a soc support. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: ls_pcie_g4: add device tree fixups for PCI Stream IDsHou Zhiqiang3-6/+251
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCsHou Zhiqiang4-0/+850
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22dm: core: Fix dm_extended_scan_fdt()Patrice Chotard1-1/+1
This function takes an argument, blob, but never uses it, instead uses gd->fdt_blob directly. Fixes: e81c98649b7a ("dm: core: add clocks node scan") Reported-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-17 12:01:30 +0300