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2019-08-30mmc: invalidate block cache after hwpart switched successfullyWeijie Gao1-1/+6
eMMC device has multiple hw partitions both address from zero. However the mmc driver lacks block cache invalidation for switch hwpart. This causes a problem that data of current hw partition is cached before switching to another hw partition. And the following read operation of the latter hw partition will get wrong data when reading from the addresses that have been cached previously. To solve this problem, invalidate block cache after a successful mmc_switch_part() operation. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Felix Brack <fb@ltec.ch>
2019-08-30Revert "blk: Invalidate block cache when switching hwpart"Weijie Gao1-12/+2
This reverts commit 0ebe112d09b48230ba4be833cd3504b06997d9a4. Most block devices have only one hwpart. Multiple hwparts only found used by eMMC devices in u-boot. The mmc driver do blk_dselect_hwpart() at the beginning of mmc_bread() which causes block cache being invalidated too frequently and makes block cache useless. So it's not a good idea to put blkcache_invalidate() in the common functions. It should be called inside mmc_select_hwpart(). Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Felix Brack <fb@ltec.ch>
2019-08-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini2-39/+92
Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
2019-08-29Merge tag 'u-boot-amlogic-20190828' of ↵Tom Rini1-0/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - add missing g12b clock driver compatible, fixing odroid-n2 usb support
2019-08-28dm: pcie_fsl: Add MPC8548 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for MPC8548 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P5040 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P5040 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P4080 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P4080 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P3041 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for P3041 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add P2041 PCIe supportHou Zhiqiang1-0/+7
Add compatible string for P2041 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCsHou Zhiqiang1-0/+7
Add compatible string for PCIe of P1020, P1021, P1024, P1025 and P2020 SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T104x PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T104x PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T102x PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T102x PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Add T4240 PCIe supportHou Zhiqiang1-0/+1
Add compatible string for T4240 PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Fix the calculation of controller indexHou Zhiqiang2-2/+19
The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Fix the Class Code fixup functionHou Zhiqiang2-4/+16
The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdefHou Zhiqiang1-33/+36
This can avoid build error: The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only defined on the platforms that select the CONFIG_FOO, while it's not defined on platforms that do not select the CONFIG_FOO. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-28clk: meson-g12b: add compatibleMark Kettenis1-0/+1
The G12B clock controller is almost identical to the G12A and so far the differences don't matter. Adding the G12B compatible makes USB work on the Odroid-N2. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-27Merge branch 'u-boot-stm32_20190827' of ↵Tom Rini14-155/+222
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Fixes and update related to STM32MP1 platforms
2019-08-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini1-43/+76
Support of device tree model for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, P5040DS and MPC8548CDS. Also support of i2c dm model.
2019-08-27stm32mp1: Add remoteproc support for m4 coprocessorPatrick Delaunay1-1/+1
Alignment with kernel patch proposal for binding: [PATCH v4 0/8] stm32 m4 remoteproc on STM32MP157c https://lkml.org/lkml/2019/5/14/159 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27misc: change RCC form MISC to NOP uclassPatrick Delaunay1-4/+1
The RCC driver have no operation so the new NOP uclass is more appropriate. It only used as parent for clock and reset driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stpmic1: simplify stpmic1_sysreset_requestPatrick Delaunay1-8/+1
Retrieve parent device from dev->parent instead of calling uclass_get_device_by_driver() Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27pmu: stpmic1: change specific NVM api to MISCPatrick Delaunay2-46/+96
Use MISC u-class to export the NVM register (starting at 0xF8 offset) and avoid specific API. - SHADOW have offset < 0. - NVM have register > 0 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27bsec: update after MISC u-class updatePatrick Delaunay1-13/+17
Since the commit 8729b1ae2cbd ("misc: Update read() and write() methods to return bytes xfered"); The misc bsec driver need to be adapted to reflect the number of transferred bytes. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: clk: use gd to store frequency informationPatrick Delaunay1-7/+9
Use existing gd structure to store frequency information which can be used in drivers or arch without new request. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: clk: remove debug tracesPatrick Delaunay1-17/+4
Remove many debug trace. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: ram: add pattern parameter in infinite write testPatrick Delaunay1-11/+20
Add pattern for infinite test_read and test_write, that allow to change the pattern to test without recompilation; default pattern is 0xA5A5AA55. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: ram: reload watchdog during ddr testPatrick Delaunay1-0/+3
Avoid watchdog during infinite DDR test. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: ram: update loop management in infinite testPatrick Delaunay1-13/+25
Reduce verbosity of the infinite tests to avoid CubeMX issue. test and display loop by 1024*1024 accesses: read or write. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: ram: fix address issue in 2 testsPatrick Delaunay1-11/+14
If user choose to test memory size is 1GByte (0x40000000), memory address would overflow in test "Random" and test "FrequencySelectivePattern". Thus the system would hangs up when running DDR test. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Bossen WU <bossen.wu@st.com>
2019-08-27stm32mp1: ram: cosmetic: remove unused prototypePatrick Delaunay1-4/+0
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27serial: stm32: add Framing error supportPatrick Delaunay2-2/+5
Add management of Bit 1 of USART_ISR = FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register (for stm32 after f4). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27mmc: stm32_sdmmc2: reload watchdogChristophe Kerello1-0/+3
This patch solves a watchdog reset issue during mmc erase command. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27pinctrl: stmfx: update pinconf settingsPatrick Delaunay1-10/+10
Alignment with kernel driver. According to the following tab (coming from STMFX datasheet), updates have to done in stmfx_pinctrl_conf_set function: -"type" has to be set when "bias" is configured as "pull-up or pull-down" -PIN_CONFIG_DRIVE_PUSH_PULL should only be used when gpio is configured as output. There is so no need to check direction. DIR | TYPE | PUPD | MFX GPIO configuration ----|------|------|--------------------------------------------------- 1 | 1 | 1 | OUTPUT open drain with internal pull-up resistor ----|------|------|--------------------------------------------------- 1 | 1 | 0 | OUTPUT open drain with internal pull-down resistor ----|------|------|--------------------------------------------------- 1 | 0 | 0/1 | OUTPUT push pull no pull ----|------|------|--------------------------------------------------- 0 | 1 | 1 | INPUT with internal pull-up resistor ----|------|------|--------------------------------------------------- 0 | 1 | 0 | INPUT with internal pull-down resistor ----|------|------|--------------------------------------------------- 0 | 0 | 1 | INPUT floating ----|------|------|--------------------------------------------------- 0 | 0 | 0 | analog (GPIO not used, default setting) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27pinctrl: pinctrl_stm32: cosmetic: Reorder include filesPatrice Chotard1-2/+2
Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27rtc: stm32: manage 2 digit limitation on yearPatrick Delaunay1-2/+7
STM32 RTC manages only 2 digits for YEAR (Year tens and units in BCD format in RTC_DR register). With this patch, RTC driver assumes that tm->tm_years is between 2000 and 2099; tm->tm_year - 2000 have only 2 digit (0 > and <= 99). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27mmc: sti_sdhci: Fix sdhci_setup_cfg() call.Patrice Chotard1-3/+3
host->mmc, host->mmc->dev and host->mmc->priv must be set before calling sdhci_setup_cfg() to avoid hang during mmc initialization. Thanks to commit 3d296365e4e8 ("mmc: sdhci: Add support for sdhci-caps-mask") which put this issue into evidence. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-27mmc: stm32_sdmmc2: Increase SDMMC_BUSYD0END_TIMEOUT_USPatrice Chotard1-1/+1
Increase SDMMC_BUSYD0END_TIMEOUT_US from 1s to 2s to avoid timeout error during blocks erase on some sdcard Issue seen on Kingston 16GB : Device: STM32 SDMMC2 Manufacturer ID: 27 OEM: 5048 Name: SD16G Bus Speed: 50000000 Mode: SD High Speed (50MHz) card capabilities: widths [4, 1] modes [SD Legacy, SD High Speed (50MHz)] host capabilities: widths [4, 1] modes [MMC legacy, SD Legacy, MMC High Speed (26MHz), SD High Speed (50MHz), MMC High Speed (52MHz)] Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.5 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes Issue reproduced with following command: STM32MP> mmc erase 0 100000 MMC erase: dev # 0, block # 0, count 1048576 ... mmc erase failed 16384 blocks erased: ERROR By setting SDMMC_BUSYD0END_TIMEOUT_US at 2 seconds and by adding time measurement in stm32_sdmmc2_end_cmd() as shown below: +start = get_timer(0); /* Polling status register */ ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask, SDMMC_BUSYD0END_TIMEOUT_US); +printf("time = %ld ms\n", get_timer(start)); We get the following trace: STM32MP> mmc erase 0 100000 MMC erase: dev # 0, block # 0, count 1048576 ... time = 17 ms time = 1 ms time = 1025 ms time = 54 ms time = 56 ms time = 1021 ms time = 57 ms time = 56 ms time = 1020 ms time = 53 ms time = 57 ms time = 1021 ms time = 53 ms time = 57 ms time = 1313 ms time = 54 ms time = 56 ms time = 1026 ms time = 54 ms time = 56 ms time = 1036 ms time = 54 ms time = 56 ms time = 1028 ms time = 53 ms time = 56 ms time = 1027 ms time = 54 ms time = 56 ms time = 1024 ms time = 54 ms time = 56 ms time = 1020 ms time = 54 ms time = 57 ms time = 1023 ms time = 54 ms time = 56 ms time = 1033 ms time = 53 ms time = 57 ms .... time = 53 ms time = 57 ms time = 1021 ms time = 56 ms time = 56 ms time = 1026 ms time = 54 ms time = 56 ms 1048576 blocks erased: OK We see that 1 second timeout is not enough, we also see one measurement up to 1313 ms. Set the timeout to 2 second to keep a security margin. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-08-27misc: i2c_eeprom: verify that the chip is functional at probe()Baruch Siach1-0/+8
Read a single byte from EEPROM to verify that it is actually there. This is equivalent to Linux kernel commit 00f0ea70d2b8 ("eeprom: at24: check if the chip is functional in probe()"). Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> hs: fixed style check prefer kernel type 'u8' over 'uint8_t'
2019-08-27i2c: mxc_i2c: Remove i2c_idle_bus from probeYe Li1-7/+0
i2c_idle_bus is already used in i2c_init_transfer. So before each transfer if the bus is not ready, the i2c_idle_bus will be used to force idle. It is unnecessary to call it again in probe. We found a issue when enabling i2c mux with the mxc_i2c. The mxc_i2c is probed after mux probing. However, at this moment the mux is still in idle state not select any port. So if we call i2c_idle_bus in probe, it will fail and cause mxc_i2c probe failed. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-08-27i2c-mux-gpio: Fix GPIO request flag issueYe Li1-1/+1
When requesting GPIO, the GPIOD_IS_OUT is missed in flag, so the GPIO is set the input mode not output and cause mux not work. Signed-off-by: Ye Li <ye.li@nxp.com>
2019-08-26Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford5-4/+7
Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-26nvme: Fix PRP Offset InvalidAaron Williams1-10/+19
When large writes take place I saw a Samsung EVO 970+ return a status value of 0x13, PRP Offset Invalid. I tracked this down to the improper handling of PRP entries. The blocks the PRP entries are placed in cannot cross a page boundary and thus should be allocated on page boundaries. This is how the Linux kernel driver works. With this patch, the PRP pool is allocated on a page boundary and other than the very first allocation, the pool size is a multiple of the page size. Each page can hold (4096 / 8) - 1 entries since the last entry must point to the next page in the pool. Signed-off-by: Aaron Williams <awilliams@marvell.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-26ddr, fsl: add DM_I2C supportHeiko Schocher1-43/+76
add DM_I2C support for this driver. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-26dm: scsi: Scan the actual number of portsPark, Aiden1-0/+8
The scsi_scan_dev() is looping over the number of uc_plat->max_id. The number of actual ports a AHCI controller has can be greater than max_id. Update uc_plat->max_id to make SCSI scan all detected ports. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-26mtd: nand: raw: Move CONFIG_SYS_NAND_USE_FLASH_BBT to KconfigStefan Roese1-0/+5
Convert CONFIG_SYS_NAND_USE_FLASH_BBT to Kconfig, update defconfigs, headers and whitelist. Please note that this symbol already was used in Kconfig (imply in CONFIG_NAND_ATMEL) which did not work, since this symbol was not available in Kconfig. This changes now with this patch and all boards with CONFIG_NAND_ATMEL will have BBT enabled. Which is what I also need on my GARDENA AT91SAM based board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> [trini: Rework such that the configs are unchanged to start with] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-24Merge tag 'u-boot-rockchip-20190823' of ↵Tom Rini2-78/+93
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - remove rk3288 fennec board - remove SPL raw image support for Rockchip SoCs - add common misc_init_r() for ethaddr from cpuid - enable USB HOST support for rk3328 - unify code for finding a valid gpt in part driver
2019-08-24Merge branch '2019-08-23-master-imports'Tom Rini2-0/+12
- Migrate CONFIG_MX_CYCLIC, CONFIG_FSL_USDHC and CONFIG_MXS_GPIO to Kconfig - Fix some SPL/TPL and ARM64 dependencies
2019-08-23Convert CONFIG_FSL_USDHC to KconfigAdam Ford1-0/+7
This converts the following to Kconfig: CONFIG_FSL_USDHC Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Add IMX8M, TARGET_S32V234EVB to FSL_USDHC list] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-23kconfig: Convert CONFIG_MXS_GPIO to KconfigLukasz Majewski1-0/+5
This converts the following to Kconfig: CONFIG_MXS_GPIO Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/571260789 Signed-off-by: Lukasz Majewski <lukma@denx.de> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
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