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2020-01-22Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2-2/+11
- Clearfog: Add run-time board detection with TLV EEPROM support (Baruch)
2020-01-21ddr: marvell: a38x: allow board specific clock out setupBaruch Siach2-2/+11
DDR clock out might be unrelated to the number of active chip-select. For example, the board might have two DDR components, but only one chip-select. The clk_enable mask allows the board to enable DDR clocks regardless of active chip-selects. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-01-20Merge tag '2020-01-20-ti-2020.04' of ↵Tom Rini8-160/+383
https://gitlab.denx.de/u-boot/custodians/u-boot-ti K3 J721E: * DMA support. * MMC and ADMA support. * EEPROM support. * J721e High Security EVM support. * USB DT nodes K3 AM654: * Fixed boot due to pmic probe error. * USB support and DT nodes. * ADMA support DRA7xx/AM57xx: * BBAI board support * Clean up of net platform code under board/ti AM33/AM43/Davinci: * Reduce SPL size for omap3 boards. * SPL DT support for da850-lcdk * PLL divider fix for AM335x
2020-01-20clk: sci-clk: add slack to clk-set-rate passed to firmwareLokesh Vutla1-2/+1
Add slack to the clock frequency parameters passed to firmware within clk_set_rate. min-freq is changed to 0 and max-rate is changed to ULONG_MAX. This fixes certain issues with pll clock rounding when the firmware is not able to set the frequency exactly to the target, the current implementation fails if the available frequency is even 1Hz off the target. With the change, the firmware still tries its best to set the frequency as close as possible to the target. Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20phy: omap-usb2-phy: Add support for AM654 USB2 PHYVignesh Raghavendra1-0/+17
AM654 SoC has USB2 PHY which is similar to existing USB2 PHYs on OMAP SoCs. Add support for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20phy: omap-usb2-phy: Fix warnings when built for ARM64Vignesh Raghavendra1-3/+2
Below warning is seen when this driver is built for devices with 64 bit physical address space. drivers/phy/omap-usb2-phy.c: In function ‘omap_usb2_phy_probe’: drivers/phy/omap-usb2-phy.c:187:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->phy_base = (void *)base; ^ Fix this by using dev_read_addr_ptr() instead of dev_read_addr(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dwc3-generic: Add support for AM654 USB controllerVignesh Raghavendra1-0/+1
AM654 has DWC3 USB controller that is very similar to other TI SoCs. Add a new compatible to enable the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20power: regulator: tps62360_regulator: Convert ofdata_to_platdata to the ↵Keerthy1-2/+2
missing probe commit 29f7d05a347a ("dm: core: Move ofdata_to_platdata() call earlier") introduces changes in the order of device_probe execution. ofdata_to_platdata now comes before the probe function which resulted in a deadlock and caused boot hang on AM6 devices. Deadlock sequence: tps62360_regulator_ofdata_to_platdata --> i2c_get_chip --> device_probe(tps62360) --> tps62360_regulator_ofdata_to_platdata Hence convert ofdata_to_platdata to the missing probe function to fix the hang. Fixes: 22e8f18980d6 ("power: regulator: tps6236x: add support for tps6236x regulators") Signed-off-by: Keerthy <j-keerthy@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20mmc: am654_sdhci: Add Support for configuring PHY in J721eFaiz Abbas1-29/+98
Add Support for writing to PHY registers for J721e. There are number of differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY. Create a driver_data structure with an ops and flags field and use the flags field to indicate these differences. The differences are as follows: 1. The J721e 4 bit instance PHY does not have a DLL. Introduce a DLL_PRESENT flag to make sure that DLL related registers are accessed only where they are present. Also add a separate set_ios_post() callback. 2. The J721e 8 bit instance is not muxed with anything else inside the SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is used to indicate the presence of this field. 3. The register field used to select DLL frequency is 3 bit wide in J721e as compared to 2 bits in AM65x. Add another flag that distinguishes these fields. 4. The strobe select field is 8 bit wide as compared to 4 bit wide for AM65x. Add yet another flag to indicate this difference. Strobe select is used only for HS400 speed mode, support for which has not been added in AM65x. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20mmc: am654_sdhci: Get Xin clock by nameFaiz Abbas1-1/+1
Get clk_xin by name instead of by index to avoid having to put clocks in the same order in all devices. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dma: ti: k3-udma: Fix build warnings when building for 32 bit platformsVignesh Raghavendra1-8/+8
Cast pointers properly so as to avoid warnings when driver is built for 32 bit platforms Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dma: ti: k3-udma: Fix ring push operation for 32 bit coresVignesh Raghavendra1-3/+11
UDMA always expects 64 bit address pointer of the transfer descriptor in the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size. Therefore copy over 32 bit pointer value to 64 bit variable before pushing it over to the ring, so that upper 32 bits are 0s. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dma: ti: k3-udma: Switch to exposed ring modeVignesh Raghavendra1-2/+2
Exposed ring mode works well with 32 bit and 64 bit cores without need for Proxies for 32 bit cores. Therefore switch to exposed ring mode. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV transfersVignesh Raghavendra1-2/+2
Fix up the debug prints that were dumping state of TCHAN RT registers to use tchan for MEM_TO_DEV transfers. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dma: ti: k3-udma: Remove coherency check for cache opsVignesh Raghavendra1-33/+16
Remove redundant coherency checks before calling cache ops in UDMA driver. This is now handled in arch specific cache operation implementation based on Kconfig option Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandleVignesh Raghavendra1-1/+2
Instead of looking getting reference to SYSFW device using name which is not guaranteed to be constant, use phandle supplied in the DT node to get reference to SYSFW Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/popVignesh Raghavendra1-0/+11
Flush caches when pushing an element to ring and invalidate caches when popping an element from ring in Exposed Ring mode. Otherwise DMA transfers don't work properly in R5 SPL (with caches enabled) where the core is not in coherency domain. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dma: ti: k3-udma: Query DMA channels allocated from Resource ManagerVignesh Raghavendra1-79/+214
On K3 SoCs, DMA channels are shared across multiple entities, therefore U-Boot DMA driver needs to query resource range from centralised resource management controller i.e SystemFirmware and use DMA channels allocated for A72 host. Add support for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20thermal: ti-bandgap: Fix adc value datatypeFaiz Abbas1-3/+3
The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to be indexed into a lookup table to get the actual temperature. Fix the naming and datatype of the adc value variable. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-18common: Move hang() to the same header as panic()Simon Glass24-0/+24
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17common: Move RAM-sizing functions to init.hSimon Glass6-0/+6
These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Rename and move source()Simon Glass1-1/+1
This function has a very generic name which does not adequately describe its purpose. Rename it and move it to image.h, since it relates to reading a script from an image. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move the image globals into image.hSimon Glass1-0/+1
These three globals relate to image handling. Move them to the image header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17image: Rename load_addr, save_addr, save_sizeSimon Glass1-3/+3
These global variables are quite short and generic. In fact the same name is more often used locally for struct members and function arguments. Add a image_ prefix to make them easier to distinguish. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move reset_cpu() to the CPU headerSimon Glass3-0/+3
Move this function out of common.h and into a relevant header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move get_tbclk() to time.hSimon Glass1-0/+1
This function related to timer and most of the timer functions are in time.h, so move this function there. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move clock functions into a new fileSimon Glass7-0/+7
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move ll_boot_init() to init.hSimon Glass2-0/+2
This is an init-related function so belongs in that file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Drop floppy disk supportSimon Glass3-107/+1
This seems pretty old now. It has not been converted to driver model and is not used by any boards. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-16Merge tag 'mmc-1-16-2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini4-70/+39
- Cleanup of fsl_esdhc driver together with arch/defconfig change - Add quirk for APP_CMD retry
2020-01-16Merge tag 'xilinx-for-v2020.04' of ↵Tom Rini6-220/+314
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.04 ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default
2020-01-16mmc: add mmc and sd support for MT7622Sam Shih1-0/+10
This patch add mmc and sd support for Mediatek MT7622 SoCs Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16power: domain: add power domain support for MT7622Sam Shih1-0/+6
This patch add power domain support for Mediatek MT7622 SoCs Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16clk: mediatek: fix clock-rate overflow problemSam Shih1-3/+3
This patch fix clock-rate overflow problem in mediatek clock driver common part. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: add driver for MT7622Sam Shih2-0/+679
This patch add clock driver for MediaTek MT7622 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16pinctrl: mediatek: add support for different pinctrlSam Shih7-19/+125
Due to the pinctrl hardware of MT7622 is difference from others SoC which using the common part of mediatek pinctrl. So we need to modify the common part of mediatek pinctrl. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16pinctrl: mediatek: add driver for MT7622Sam Shih3-0/+757
This patch add Pinctrl driver for MediaTek MT7622 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16phy: phy-mtk-tphy: make ref clock optionalChunfeng Yun1-1/+2
If make the ref clock optional, no need refer to fixed-clock when the ref clock is always on or comes from oscillator directly. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16phy: phy-mtk-tphy: remove the check of -ENOSYSChunfeng Yun1-2/+1
No need check -ENOSYS anymore after add dummy_enable() for fixed-clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: fixed_rate: add dummy enable() functionChunfeng Yun1-0/+7
This is used to avoid clk_enable() return -ENOSYS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: add APIs to get (optional) clock by name without a deviceChunfeng Yun1-0/+28
Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: check valid clock by clk_valid()Chunfeng Yun1-8/+8
Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: fix error check for devm_clk_get_optional()Chunfeng Yun1-1/+1
If skip all return error number, it may skip some real error cases, so only skip the error when the clock is not provided in DTS Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: mt7629: add support for ssusbsysChunfeng Yun1-0/+42
The SSUSB IP's clocks come from ssusbsys module on mt7629, so add its driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16mmc: mtk-sd: fix hang when data read quicklymingming lee1-5/+1
For CMD21 tuning data, the 128/64 bytes data may coming in very short time, before msdc_start_data(), the read data has already come, in this case, clear MSDC_INT will cause the interrupt disappear and lead to the thread hang. the solution is just clear all interrupts before command was sent. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCsmingming lee1-33/+101
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs. MT8512/MT8110 SoCs puts the tune register at top layer, so need add new code to support it. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16pinctrl: mediatek: add driver for MT8512mingming lee3-0/+392
Add Pinctrl driver for MediaTek MT8512 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pllmingming lee2-8/+20
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
2020-01-16clk: mediatek: add set_clr_upd mux type flowmingming lee2-11/+55
Add new set_clr_upd mux type and related operation to mtk common clock driver to support mt8512
2020-01-16clk: mediatek: add driver support for MT8512mingming lee2-0/+874
Add clock driver for MediaTek MT8512 SoC, include topckgen, apmixedsys and infracfg support. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-08 16:33:28 +0300