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2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass910-1255/+1251
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Drop unused parameter from dm_extended_scan_fdt()Simon Glass1-3/+3
This doesn't need to be passed the devicetree anymore. Drop it. Also rename the function to drop the _fdt suffix. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Drop unused parameter from dm_scan_fdt()Simon Glass1-5/+4
This doesn't need to be passed the devicetree anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Combine the flattree and livetree binding codeSimon Glass1-58/+16
At present there are two copies of this code. With ofnode we can combine them to reduce duplication. Update the dm_scan_fdt_node() function and adjust its callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Add an ofnode function to get the devicetree rootSimon Glass1-6/+2
This is needed in at least one place. Avoid the conditional code in root.c by adding this inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Drop device_bind_offset()Simon Glass1-8/+0
This function is not needed since the standard device_bind() can be used instead. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: Drop uses of dev_set_of_offset()Simon Glass6-13/+6
The need for this can be avoided by passing the correct node to the device_bind() function. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: Remove uses of device_bind_offset()Simon Glass17-45/+42
This function is not needed since the standard device_bind() can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Add a livetree function to check node statusSimon Glass1-0/+10
Add a way to find out if a node is enabled or not, based on its 'status' property. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind_ofnode() to device_bind()Simon Glass8-16/+16
This is the standard function to use when binding devices. Drop the '_ofnode' suffix to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind() to device_bind_offset()Simon Glass17-31/+33
This function is not necessary anymore, since device_bind_ofnode() does the same thing and works with both flattree and livetree. Rename it to indicate that it is special. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13sandbox: serial: Update to use membuffSimon Glass1-29/+19
Rather than implementing our own circular queue, use membuff. This allows us to read multiple bytes at once into the serial input. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13sandbox: serial: Convert to livetreeSimon Glass1-3/+1
Use a livetree function to read the colour. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13serial: sandbox: Drop unnecessary #ifdefsSimon Glass1-9/+2
CONFIG_OF_CONTROL is always enabled for sandbox (as it should be for all boards), so we can drop it. Also use IS_ENABLED() for the SPL check. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-01gpio: Convert to use APIs which support live DTPatrick Delaunay1-3/+2
Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-11-29Merge tag 'mmc-2020-11-29' of ↵Tom Rini2-94/+91
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - mmc minor update for better debug and error check - fsl_esdhc sysctl set and make sure delay check for HS400
2020-11-28i2c: ocores: add i2c driver for OpenCores I2C controllerPragnesh Patel3-0/+645
Add support for the OpenCores I2C controller IP core (See http://www.opencores.org/projects.cgi/web/i2c/overview). This driver implementation is inspired from the Linux OpenCores I2C driver available. Thanks to Peter Korsgaard <peter@korsgaard.com> for writing Linux OpenCores I2C driver. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-11-28i2c: designware_i2c: Don't warn if no reset controllerSimon Glass1-3/+5
At present if CONFIG_RESET is not enabled, this code shows a warning: designware_i2c_ofdata_to_platdata() i2c_designware_pci i2c2@16,0: Can't get reset: -524 Avoid this by checking if reset is supported, first. Fixes: 622597dee4f ("i2c: designware: add reset ctrl to driver") Signed-off-by: Simon Glass <sjg@chromium.org>
2020-11-28i2c: mvtwsi: disable i2c slave also on Armada 8kBaruch Siach1-1/+2
The hidden I2C slave is also present on the Armada 8k AP806. Testing shows that this I2C slave causes the same issues as Armada 38x. Disabling that I2C slave fixes all these issues. I2C blocks on the Armada 8k CP110 are not affected. Extend the I2C slave disable to Armada 8k as well. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-11-28mmc: check a return value about regulator's always-onJaehoon Chung1-2/+2
Regulator can be set to "always-on". It's not error about enable/disable. It needs to check about its condition. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-11-28mmc: display an error number to debugJaehoon Chung1-5/+5
It's useful to know an error number when it's debugging. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-11-28mmc: fsl_esdhc: make sure delay chain locked for HS400Yangbo Lu1-3/+25
For eMMC HS400 mode, the DLL reset is a required step for mmc rescan. This step has not been documented in reference manual, but the RM will be fixed sooner or later. In previous commit to support eMMC HS400, db8f936 mmc: fsl_esdhc: support eMMC HS400 mode the steps to configure DLL could be found in commit message, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. these would be fixed as, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us, then write DLLCFG0[DLL_RESET] 14. Wait for delay chain to lock. This patch is to add the step of DLL reset, and make sure delay chain locked for HS400. Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28mmc: fsl_esdhc: set sysctl register for clock initializationYangbo Lu1-1/+1
The initial clock setting should be through sysctl register only, while the mmc_set_clock() will call mmc_set_ios() introduce other configurations like bus width, mode, and so on. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28mmc: Add some helper functions for retrying on errorSean Anderson1-83/+58
All of the existing quirks add retries to various calls of mmc_send_cmd. mmc_send_cmd_quirks is a helper function to do this retrying behavior. It checks if quirks mode is enabled, and if a specific quirk is activated it retries on error. This also adds mmc_send_cmd_retry, which retries on error every time (instead of if a quirk is activated). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-25phy: stm32: usbphyc: manage optional vbus regulator on phy_power_on/offPatrick Delaunay1-10/+23
This patch adds support for optional vbus regulator. It is managed on phy_power_on/off calls and may be needed for host mode. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25pinctrl: stmfx: update pin namePatrick Delaunay1-4/+4
Update pin name to avoid duplicated name with SOC GPIO gpio0...gpio15 / agpio0....agpio7: add a stmfx prefix. This pin name can be used in pinmux command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25pinctrl: stmfx: update pincontrol and gpio device namePatrick Delaunay1-1/+4
The device name is used in pinmux command and in log trace so it is better to use the parent parent name ("stmfx@42" for example) than a generic name ("pinctrl" or "stmfx-gpio") to identify the device instance. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25gpio: stm32: correct the bias managementPatrick Delaunay1-14/+14
Use the bias configuration for all the GPIO configurations and not only for input GPIO, as indicated in Reference manual (Table 81. Port bit configuration table). Fixes: 43efbb6a3ebf0223f9eab8d45916f602d876319f ("gpio: stm32: add ops get_dir_flags") Fixes: f13ff88b61c32ac8f0e9068c41328b265ef619eb ("gpio: stm32: add ops set_dir_flags") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25pinctrl: stm32: display bias information for all pinsPatrick Delaunay1-12/+12
Display the bias information for input gpios or AF configuration, and not only for output pin, as described in Reference manual (Table 81. Port bit configuration table). Fixes: da7a0bb1f279 ("pinctrl: stm32: add information on pin configuration") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25remoteproc: stm32: update error management in stm32_copro_startPatrick Delaunay1-7/+6
The coprocessor is running as soon as the hold boot is de-asserted. So indicate this running state and save the resource table even if the protective assert, to avoid autonomous reboot, is failed. This error case should never occurs. Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25remoteproc: stm32: use reset for hold bootPatrick Delaunay1-68/+25
Use the reset function to handle the hold boot bit in RCC with device tree handle with MCU_HOLD_BOOT identifier. This generic reset allows to remove the two specific properties: - st,syscfg-holdboot - st,syscfg-tz This patch prepares alignment with kernel device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25reset: stm32: Add support of MCU HOLD BOOTPatrick Delaunay1-4/+13
Handle the register RCC_MP_GCR without SET/CLR registers but with a direct access to bit BOOT_MCU: - deassert => set the bit: The MCU will not be in HOLD_BOOT - assert => clear the bit: The MCU will be set in HOLD_BOOT With this patch the RCC driver handles the MCU_HOLD_BOOT_R value added in binding stm32mp1-resets.h Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-22Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbTom Rini3-23/+42
- DWC2, DWC3 fixes
2020-11-22usb: gadget: dwc2_udc_otg: return zero when reset property is not presentJaehoon Chung1-1/+1
If reset DT property is not present, -ENOENT is returned. But it's not really error. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-22usb: dwc3: Handle case where setup_phy is not neededSiva Durga Prasad Paladugu1-1/+1
If CONFIG_PHY is not enabled then the dwc3_setup_phy() returns ENOTSUPP which can be still valid and intentional so modify error check to handle this -ENOTSUPP. The same error handling exists in drivers/usb/host/xhci-dwc3.c already added by commit d648a50c0a27 ("dwc3: move phy operation to core.c"). Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-11-22usb: dwc2: add "u-boot,force-vbus-detection" for stm32Patrick Delaunay2-21/+40
On some board, the ID pin is not connected so the B session must be overridden with "u-boot,force_b_session_valid" but the VBus sensing must continue to be handle. To managed it, this patch adds a new DT field "u-boot,force-vbus-detection" to use with "u-boot,force_b_session_valid" Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-22pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrlLad Prabhakar1-4/+0
Drop unused members from struct sh_pfc_pinctrl. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-11-22pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A774E1Biju Das1-2/+12
This driver supports both RZ/G2H and R-Car H3 SoCs. Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 (R8A7795) is not enabled Based on the similar patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-11-22pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1Biju Das1-0/+12
This driver supports both RZ/G2N and R-Car M3-N SoCs. Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N (R8A77965) is not enabled. Based on the simialr patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-11-22pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1Biju Das1-0/+12
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs. Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+ (R8A7796[01]) is not enabled. Based on the similar patch on Linux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-11-22pinctrl: renesas: r8a77951: Add R8A774E1 PFC supportBiju Das5-409/+519
Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951), however it doesn't have several automotive specific peripherals. Add a r8a77951 specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-11-22pinctrl: renesas: r8a77965: Add R8A774B1 PFC supportBiju Das5-405/+513
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-11-21Merge tag 'efi-2021-01-rc3-2' of ↵Tom Rini1-2/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2021-01-rc3 (2) The parameter check for UEFI service GetNextVariableName() is corrected. The dependencies of CONFIG_DFU_TFTP are simplified. The set of supported hash algorithms reported by the EFI_TCG2_PROTOCOL is corrected.
2020-11-21dfu: simplify the dependencies of DFU_TFTPAKASHI Takahiro1-2/+1
Since CONFIG_UPDATE_COMMON always selects CONFIG_DFU_WRITE_ALT, we can drop the latter from dependencies of CONFIG_DFU_TFTP. Fixes: 3149e524fc1e ("common: update: add a generic interface for FIT image") Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-11-20tpm: spi: Cleanup source codeMichal Simek1-3/+0
There is no need for GD to be used and priv variable is unused. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-11-19drivers: led: bcm6858: set the correct led polarity registerSteven Lawrance1-4/+4
This change sets the output (hardware) polarity register instead of the input (software) polarity register for the bcm6858 LED controller. The logic was inverted (a LED configued active high behaved as active low). Signed-off-by: Steven Lawrance <steven.lawrance@softathome.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-11-17Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini1-9/+12
- Enable SATA disk on QEMU RISC-V and update doc. - k210 pinctrl updates: - Fix inverted IE and OE for I2C. - Rename power domains to match datasheet.
2020-11-17pinctrl: k210: Rename power domains to match datasheetSean Anderson1-5/+5
This renames power domains to match the names on the k210 datasheet. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-11-17pinctrl: k210: Fix inverted IE and OE for I2CSean Anderson1-4/+7
I2C and SCCB previously shared defaults. However, SCCB needs OE_INV and IE_INV set, but I2C cannot have those bits set. This adds a separate default for SCCB. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
2020-11-17sunxi: allow to use AXP20[39] attached to I2C0 on V3 seriesIcenowy Zheng1-2/+2
The reference design of Allwinner V3 series uses an AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the first community-available V3s board, Lichee Pi Zero, omitted it. Allow to introduce support for the PMIC on boards with it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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