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Correct the parent of i2c clocks and add full i2c clocks.
The code mainly is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Make the code be compatible with the StarFive VisionFive 2 board.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Make the code be compatible with the StarFive VisionFive 2 board.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Make the code be compatible with the StarFive VisionFive 2 board.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: Samin Guo <samin.guo@linux.starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Make the code be compatible with the StarFive VisionFive 2 board.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Add SYS_I2C_DW driver to support in SPL.
Signed-off-by: Yanhong Wang <yanhong.wang@linux.starfivetech.com>
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xhci_wait_for_event() wait TRB_TRANSFER may return null
pointer, shoud checkit avoid crash.
Read usb device info maybe failed, should check it and
do not register usb device. uboot should rescan usb
device and register.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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CR 7124 PCIe dts & driver: Modified reset & link wait timing for better compatbility.
See merge request sdk/u-boot!71
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1. Modified reset assert duration to 100ms.
2. Wait 10-100 ms for link training.
3. If link is up, delay 100ms before doing any configuration space access.
Reference spec: PCIe Base Spec r6.0 & CEM 2.0.
Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
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the vout clocks on enable status, when no connecters (hdmi or mipi)
this will cause emmc init many times
need to closed the vout clocks
Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
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Add config for max block size to write in MMC with sparse file.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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Add a new parameter to get "logical-block-size" in getvar command.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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Add new flag to load image file to preset address without partition.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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Add USB device support. Add dr_num_mode for
changing the dr mode number, For changing the strings cause issues.
For devkits, If using device,
need to changed starfive,usb2-only to 1 and dr_num_mode
to 2.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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CR_7199 usb: cdns3: starfive: Add usb driver to support for JH7110
See merge request sdk/u-boot!66
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Add usb driver to support for jh7110.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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Set SS EP config bit by USB SS speed. Avoid transfer
timeout.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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CR_6570: mmc: starfive: add HS200 support
See merge request sdk/u-boot!62
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fix mmc device power-up sequence.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
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Add tuning and other related code to the driver to support HS200 mode.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
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subtract the root bus number to get the correct
config addr.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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dram_init call fdtdec_setup_mem_size_base, so starfive_ddr.c do not
need it.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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CR6604:dram: jh7110: sync from devkits/vf2
See merge request sdk/u-boot!59
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Add ddr4 tuning support (sync from devkits)
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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The hdmi display is unstable after repeated reset
blank panel or write panel
Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
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add 1G DDR tuning cfg
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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CR5042: net: phy: motorcomm: add Pad Drive Strength Cfg
See merge request sdk/u-boot!52
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Unify the content format of the copyright section
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
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YT8531 supports Pad Drive Strength configuration.
Including rx_data/rx_clk, etc.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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The default configuration of the SIFIVE L2 Prefetcher may not be the
best combination on the JH7110, and some parameters need to be modified
to achieve the best performance.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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Support getting direction of gpio.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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starfive_pinctrl_priv struct is a priv of the parent
device (pinctrl device), not the gpio device.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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hdmi can show a bitmap logo while uboot start
and the default resolution is 1920x1080@60fps
Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
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As the i2c_designware_pci.c uses ACPI APIs,
add the ACPI table generation configuration
for its compilation.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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Add the NIC device ID and adjust the bar regions.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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Add the stg clocks for PCIe controller.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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Port the JH7110 pcie host driver from linux kernel.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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add vout mipi pipeline driver in uboot
Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
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add clock config for i2c2 and i2c5
update the i2c driver clock config
Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
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add power subsystem in driver,include pmu pmic and regulator
pmu : dc8200 power
pmic : mipi power
regulator : entend power
Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
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Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
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CR_3006 misc: OTP: Starfive-jh7110: update the return value of starfive_otp_read
See merge request sdk/u-boot!21
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Add vout clock driver for StarFive JH7110
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
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Update the return value to match the function prototype definition.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
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Add pinctrl driver for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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support use original or inverted RGMII_TX_CLK delay train.
10M/100M/1000M can be configured independently.
tx_inverted_xx = val;
For example:
&gmac0 {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
tx_inverted_10 = <0>;
tx_inverted_100 = <1>;
tx_inverted_1000 = <1>;
};
};
0: original (default)
1: inverted
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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This patch include four items:
1.rename the driver compatible name.
2.reset action with the common API.
3.clean up code to make it is closer to readable.
4.add configuration to support 8G size
Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
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Replace the configuration operation for pll1 clk with common api provide
by pll module.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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The previous definition of apb_bus clock relationship is incorrect,so
update it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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