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2021-01-31sandbox: keep time offset when resettingHeinrich Schuchardt1-1/+3
The UEFI Self Certification Test (SCT) checks the SetTime() service with the following steps: * set date * reset * check date matches To be compliant the sandbox should keep the offset to the host RTC during resets. The implementation uses the environment variable UBOOT_SB_TIME_OFFSET to persist the offset. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-31dm: core: Update ofnode_read_fmap_entry() to read hashesSimon Glass1-9/+12
At present this function uses the old format for reading hashes. Add support for the current format. Add a test while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31dm: core: Add a comment about pinctrl_select_state()Simon Glass1-0/+9
The use of pinctrl in the core of driver model is useful but can provoke some strange behaviour. Add a comment to aid debugging. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31clk: x86: Correct the driver nameSimon Glass1-2/+2
The current driver name does not match its compatible string, so of-platdata does not work correctly. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31clk: Add debugging for return valuesSimon Glass1-5/+11
Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31sandbox: Disable I2C emulators in SPLSimon Glass1-0/+2
These cannot work with of-platdata since they currently need the devicetree at runtime. Disable the emulators and the sandbox I2C driver that needs them. We can enable these later, if needed for testing. Switch the of_plat_parent test over to use a simple bus instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-01-31i2c: desigware: Add an alias for Intel Apollo LakeSimon Glass1-0/+2
Add an alias so that this driver can be used in TPL on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-01-31cros_ec: Add vstore supportSimon Glass2-2/+121
The EC can store small amounts of data for the benefit of the verified boot process. Since the EC is seldom reset, this can allow the AP to store data that survives a reboot or a suspend/resume cycle. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31cros_ec: Allow use with of-platdataSimon Glass1-0/+2
Avoid reading the device tree when of-platdata is in use. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31cros_ec: Show events in human-readable formSimon Glass1-1/+11
Add a command to show the current events as a list of names. This is easier to decipher than a bit mask. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31cros_ec: Add support for switchesSimon Glass3-0/+33
On x86 platforms the EC provides a way to read 'switches', which are on/off values determined by the EC. Add a new driver method for this and implement it for LPC. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31cros_ec: Support reading EC featuresSimon Glass2-6/+31
The EC can support a variety of features and provides a way to find out what is available. Add support for this. Also update the feature list to the lastest available while we are here. This is at: https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/master/include/ec_commands.h Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31cros_ec: Add support for reading the SKU IDSimon Glass2-0/+20
This allows reading strapping pins attached to the EC. Add an implementation for this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31cros_ec: Add run-time check for input buffer overflowSimon Glass1-0/+2
This should not happen in normal operation, but the EC might have a bug, so add a run-time check just in case. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31cros_ec: Tidy up a few delaysSimon Glass1-7/+17
Allow a longer time for the EC to reboot. Also use a constant for the hash delay time, so it is clear what it is for. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31cros_ec: Add a function for the hello messageSimon Glass2-15/+43
This is used several times in this file. Put it in a function to avoid code duplication. Also add a test for this function. There are no cros_ec tests at present, so it is time to update the code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31tpm: cr50: Rename driver to work with of-platdataSimon Glass1-2/+2
Update the driver name to match the compatible string, so it can work with of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31tpm: cr50: Add a better description and more debugSimon Glass1-4/+18
Update the TPM description to include the interrupt mechanicm since this is useful to know. Also add a warning if the TPM cannot be found and a debug line if it succeeds. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31tpm: cr50: Check for valid localitySimon Glass1-4/+12
When the Cr50 starts up it doesn't have a valid locality. The driver sets it to -1 to indicate that. Tracking this allows cr50_i2c_cleanup() to avoid releasing a locality that was not claimed. However the helper functions that generate the flags use a u8 type which cannot support -1, so they return a locality of 0xff. Fix this by updating the type. With this, 'tpm startup TPM2_SU_CLEAR' works as expected. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-29spi: mtk_snor: add support for MTK SPI NOR controllerSkyLake.Huang3-0/+571
This patch adds support for MTK SPI NOR controller, which you can see on mt7622 & mt7629. 1. This controller is designed only for SPI NOR. We can't adjust its bus clock dynamically. Set clock in dts instead. 2. This controller only supports 1-1-1 write mode. 3. Remove mtk_snor_match_read() since upper SPI-MEM layer already handles command. 4. sf read/write/update commands are tested with this driver. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
2021-01-28rtc: add rtc-abx80x, a driver for the Abracon AB x80x i2c rtcYing-Chun Liu (PaulLiu)3-0/+563
This is a basic driver for the ultra-low-power Abracon AB x80x series of RTC chips. It supports in particular, the supersets AB0805 and AB1805. It allows reading and writing the time, and enables the supercapacitor or battery charger. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
2021-01-28mmc: pci_mmc: Set the removable flagSimon Glass1-0/+8
Set this flag so that it is available to those looking at the device. For non-removable devices there is no need to check for insertion/removable since the media can never change. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-28mmc: pci_mmc: Only generate ACPI code for the SD cardSimon Glass1-1/+10
At present if an eMMC part is in the system, the ACPI table generated will include information about that, as well as the SD card. We only need to include the SD card, since it has a card-detect GPIO. Use a different compatible string for each option, and add code only for the SD card. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-28video: Allow syncing the entire framebuffer to the copySimon Glass1-0/+10
In some cases so much of the framebuffer is updated that it is not worth copying the changes piece by piece to the copy framebuffer. Add a function to copy the whole thing. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-28pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more)Stefan Roese2-81/+41
This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-28bootcount: allow to use this feature on TPLPhilippe Reynes1-0/+1
This commit add an option TPL_BOOTCOUNT_LIMIT to use bootcount on TPL. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini6-11/+62
- Espressobin: Disable slot when emmc is not present (Pali) - DS414; config header cleanup (Phil) - PCI: auto-config enhancement (Phil) - pci_mvebu: Also map IO region (Phil) - serial: a3720: Implement pending method for output direction (Pali) - turris_mox: Enable a few commands (Marek) - helios4 & ClearFog changes (Dennis) - Plus some minor misc changes
2021-01-27net: phy: micrel: Try default PHY ofnode firstMarek Vasut1-2/+7
The phydev structure has a PHY OF node pointer in it, use that OF node first when looking up PHY OF node properties, since that is likely the correct PHY OF node pointer. If the pointer is not valid, which is the case e.g. on legacy DTs, fall back to parsing MAC ethernet-phy subnode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
2021-01-27net: phy: ca_phy: Add driver for CAxxxx SoCsAbbie Chang4-0/+144
Add phy driver support for MACs embedded inside Cortina Access SoCs Signed-off-by: Abbie Chang <abbie.chang@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Tom Rini <trini@konsulko.com> CC: Aaron Tseng <aaron.tseng@cortina-access.com> Moved out PHY specific code out of Cortina NI Ethernet driver and into a Cortina Access PHY interface driver
2021-01-27net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCsAaron Tseng4-0/+1512
Add Cortina Access Ethernet device driver for CAxxxx SoCs. This driver supports both legacy and DM_ETH network models. Signed-off-by: Aaron Tseng <aaron.tseng@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Signed-off-by: Abbie Chang <abbie.chang@cortina-access.com> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Abbie Chang <abbie.chang@Cortina-Access.com> CC: Tom Rini <trini@konsulko.com>
2021-01-27net: e1000: Add missing address translationsStefan Roese1-5/+5
Add some missing address translations from virtual address in local DRAM to physical address, which is needed for the DMA transactions to work correctly. This issue was detected while testing the e1000 driver on the MIPS Octeon III platform, which needs address translation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2021-01-27net: e1000: Use virt_to_phys() instead of pci_virt_to_mem()Stefan Roese1-7/+1
Using (dm_)pci_virt_to_mem() is incorrect to translate the virtual address in local DRAM to a physical address. The correct macro here is virt_to_phys() so switch to using this macro. As virt_to_bus() is now not used any more, this patch also removes both definitions (DM and non-DM). This issue was detected while testing the e1000 driver on the MIPS Octeon III platform, which needs address translation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2021-01-27net: e1000: Remove unused bus_to_phys() macroStefan Roese1-2/+0
bus_to_phys() is defined but not referenced at all. This patch removes it completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2021-01-27arm64: a37xx: pci: Fix printing debug messagesPali Rohár1-3/+2
Value pcie->dev in function pcie_advk_probe() is not initialized yet so use dev as argument for dev_dbg()/dev_warn(). Function pcie_advk_wait_pio() itself prints error message on failure so do not print duplicate error message in caller. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-27serial: a3720: Implement pending method for output directionPali Rohár1-2/+8
To check if some output characters are waiting either in Transmitter Holding Register or Transmitter Shift Register we need to look at TX_EMPTY bit of UART Status Register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-27pci: pci_mvebu: Define an IO region as wellPhil Sutter1-1/+27
Configure an IO region and window for PNP identical to how MEM region is set up. Linux does this only if the DT defines a pcie-io-aperture property for the SOC, but since all supported boards do this should not be needed. Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-27pci: Make auto-config code a little more robustPhil Sutter1-4/+5
On my DS414, some PCI devices return odd values when probing BAR sizes. An obvious case is all-ones response, the Linux driver (drivers/pci/probe.c) catches those explicitly and a comment explains that either bit 0 or bit 1 must be clear (depending on MEM or IO type). Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break size calculation due to the "middle" zeroes. Mitigate that copying more or less what Linux does and do a "find least bit set". Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-27arm: mvebu: Espressobin: Disable slot when emmc is not presentPali Rohár1-0/+19
This change extends previous commit 061c6d1b238a ("arm: mvebu: Espressobin: Detect presence of emmc at runtime") and when emmc is not present then emmc is removed from U-Boot DM and corresponding slot is disabled. Therefore on Espressobin board without soldered emmc, state of emmc hw should be same as if emmc was disabled in DTS. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-27gpio: Add support for DM GPIO for KirkwoodHarm Berntsen1-1/+1
The Armada driver also works on Nedap's custom Kirkwood board with a Marvell 88F6180 CPU. The original commit of that driver, commit 704d9a645e17 ("gpio: Add DM GPIO driver for Marvell MVEBU"), also mentions that this driver would be suitable for Kirkwood. This does not completely replace the Kirkwood specific driver as there are still boards depending on that driver. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Stefan Roese <sr@denx.de>, Reviewed-by: Stefan Roese <sr@denx.de>
2021-01-26Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini10-69/+260
- New Allwinner H616 SoC support (sans Ethernet & USB) - H6 DT update - Tanix TX6 TV box support - OrangePi 3 support - OrangePi Zero2 (H616) support
2021-01-26clk: sunxi: Add support for H616 clocksJernej Skrabec3-0/+128
This commit introduces DM H616 clock driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-26sunxi: gpio: introduce compatible for H616Jernej Skrabec1-0/+2
H616 pinctrl is no different configuration wise than others, so just add compatible for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-26sunxi: Add support for H616 SoCJernej Skrabec1-0/+1
H616 is very similar to H6 so most of the infrastructure can be reused. However, two big differences are that it doesn't have functional SRAM A2 which is usually used for TF-A and it doesn't have ARISC co-processor. It also needs bigger SPL size - 48 KiB. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-26mmc: sunxi: Refactor mod clock register offsetAndre Przywara1-61/+23
So far the only difference between the various Allwinner MMC controller we are concerned about is the mod clock register offset. This is actually not directly related to the MMC controller IP, but an integration choice, dependent on the SoC this appears in. To avoid becoming trapped with some compatible fallback strings, let's remove the whole struct sunxi_mmc_variant, and replace this with a SoC based choice, which we can derive from the CONFIG_MACH_SUNx_y symbols. This will later simplify H616 support. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-01-26i2c: mvtwsi: sunxi: update macroJernej Skrabec1-1/+1
While currently none of the newer Allwinner SoCs currently has I2C support implemented in U-Boot, this will change soon. mvtwsi driver is good as it is for them except one macro. Update it to be ready once I2C support lands for those SoCs. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-26mmc: sunxi: Replace H6 ifdefs with H6 gen macroJernej Skrabec1-6/+6
It turns out that several SoCs share same mmc configuration as H6. In order to lower ifdef clutter replace H6 specific macro with common one. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-26sunxi: Add support for AXP305 PMICJernej Skrabec3-1/+96
This PMIC can be found on H616 boards and it's very similar to AXP805 and AXP806. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-26net: sun8i-emac: Allow all RGMII PHY modesAndre Przywara1-0/+3
So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-25Merge tag 'mips-pull-2021-01-24' of ↵Tom Rini25-12/+2709
https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: add support for Mediatek MT7620 SoCs
2021-01-25Merge tag 'u-boot-imx-20210125' of ↵Tom Rini7-7/+136
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Changes for 2020.04 ------------------- - new board: Phytec phyCORE-i.MX8MP i.MX8MN Beacon EmbeddedWorks devkit - Fixes: several nanbcb fixes fix for imx8mm_beacon - further switch to distro boot commands - DM: DM Ether for MX6UL CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-05 00:21:43 +0300