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path: root/include/configs/coreboot.h
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2018-08-20x86: coreboot: Add generic coreboot payload supportBin Meng1-0/+32
Currently building U-Boot as the coreboot payload requires user to change the build configuration for a specific board during menuconfig process. This uses the board's native device tree to configure the hardware. For example, the device tree provides PCI address range for the PCI host controller and U-Boot will re-program all PCI devices' BAR to be within this range. In order to make sure we don't mess up the hardware, we should guarantee the range matches what coreboot programs the chipset. But we really should make the coreboot payload support easier. Just like EFI payload, we can create a generic coreboot payload for all x86 boards as well. The payload is configured to include as many generic drivers as possible. All stuff that touches low level initialization are not allowed as such is the coreboot's responsibility. Platform specific drivers (like gpio, spi, etc) are not included. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-01-13x86: Remove include/configs/coreboot.hBin Meng1-70/+0
Since we already swtiched to use the new mechanism for building U-Boot for coreboot, coreboot.h is no longer needed so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: coreboot: Move coreboot-specific defines from coreboot.h to KconfigBin Meng1-5/+0
There are many places in the U-Boot source tree which refer to CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT that is currently defined in coreboot.h. Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch to board configuration file to build U-Boot later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-19x86: Rename coreboot-serial to x86-serialBin Meng1-1/+1
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-11-21x86: config: Move common x86 configs to a common fileSimon Glass1-256/+9
Many of the x86 CONFIG options will be common across different boards. Move them to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-10-29x86: config: Increase CONFIG_SYS_BOOTM_LEN to 16MBSimon Glass1-1/+2
The code density of x86_64 is not wonderful. Increase the maximum boot size and adjust the load address to cope. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-29x86: Display basic CPU information on bootSimon Glass1-0/+1
Display the type of CPU (x86 or x86_64) when starting up. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-24dm: x86: Convert coreboot serial to use driver modelSimon Glass1-11/+7
This makes use of the existing device tree node to use driver model for the serial console. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-24dm: x86: Convert Intel ICH6 GPIO driver to use driver modelSimon Glass1-0/+4
Convert over this driver, using device tree to pass in the required information. The peripheral is still probed, just the number of GPIO banks and their offsets is in the device tree (previously this was a table in the driver). Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23x86: Enable FIT, ELF on corebootSimon Glass1-1/+3
Enable FIT support and the bootelf command. Also change the default load address to somewhere other than the normal load address of the kernel, to allow for decompression without overwriting the original file. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23x86: config: link: Display the board model on the screenSimon Glass1-0/+1
To get a display in U-Boot on link you must either build a coreboot that always sets it up, or use Esc-Refresh-Power to reset the machine. When we do have a display, it is nice to display the model at the top, so enable this option. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23x86: link: Tidy up the command lines optionsSimon Glass1-3/+3
We may as well use hush. The auto-complete option was incorrect so this was not enabled. Also expand the command line size a little and go back to the default prompt since "boot>" doesn't seem any more useful. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23x86: cros_ec: Enable cros_ec for linkSimon Glass1-0/+5
Add defines to enable the Chrome OS EC interface and set it up on init. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23x86: config: Enable dhcp on linkSimon Glass1-0/+6
The dhcp option is required to get bootp to work on the Chromebook Pixel, so enable it. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-25kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfigMasahiro Yamada1-1/+0
This option specifies the default Device Tree used for the run-time configuration of U-Boot. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Michal Simek <michal.simek@xilinx.com>
2014-09-25kconfig: move CONFIG_OF_* to KconfigMasahiro Yamada1-2/+0
This commit moves: CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_OF_EMBED CONFIG_OF_HOSTFILE Because these options are currently not supported for SPL, the "Device Tree Control" menu does not appear in the SPL configuration. Note: zynq-common.h should be adjusted so as not to change the default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20fpga: Guard the LOADMK functionality with CMD_FPGA_LOADMKSiva Durga Prasad Paladugu1-0/+1
Guard the LOADMK functionality with config to provide an option to enable or disable it. Enable it for all platforms in mainline which enable CONFIG_CMD_FPGA. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-12-13kgdb: configs: remove obsolete CONFIG_KGDB_SER_INDEXVladimir Zapolskiy1-1/+0
The last users of CONFIG_KGDB_SER_INDEX were removed more than 3 years ago in commits 550650ddd0 and bf16500f79, either kgdb subsystem should care about this parameter or it should be gone completely. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2013-11-04config: remove platform CONFIG_SYS_HZ definition part 2/2Rob Herring1-1/+0
Remove platform CONFIG_SYS_HZ definition for configs a-z*. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-10-15Coding Style cleanup: remove trailing white spaceWolfgang Denk1-1/+1
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-09-06ahci: convert to use libata functions and definitionsRob Herring1-0/+1
libata already has similar functions as implemented in the ahci code. Refactor the code to use the libata variants and remove the dependency on ata.h. Convert some defines to use the version from libata.h. Also, remove some unnecessary memset's of bss data. This is a step toward hopefully merging ahci.c and dw_ahsata.c which are essentially the same driver. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk1-17/+1
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-06-26x86: config: Add tracing optionsSimon Glass1-0/+7
Add configs to enable tracing when it is needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-03x86: config: Reflect the name changes of LPC TPM configsTom Wai-Hong Tam1-1/+2
The new name is more aligned with Linux kernel's naming of TPM driver. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-05-14x86: config: Enable LZO for coreboot, remove zlib, gzipSimon Glass1-0/+4
We don't use zlib and gzip but do use lzo, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-14x86: Enable bootstage for corebootSimon Glass1-0/+9
This is a convenient way of finding out where boottime is going. Enable it for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-14x86: Re-enable PCAT timer 2 for beepingSimon Glass1-0/+1
While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-14x86: Add TSC timerSimon Glass1-3/+1
This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>
2013-04-16x86: config: Init PCI before SPISimon Glass1-0/+1
Since the ICH SPI controller uses PCI, we must ensure that PCI is available before it is inited. This fixes the current "ICH SPI: Cannot find device" message on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-20Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini1-3/+11
2013-03-19x86: Enable time command for corebootSimon Glass1-0/+2
This command is useful for measuring SPI flash load times and the like. Enable gettime as well to obtain absolute time tick values. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19x86: Enable SPI flash support for corebootSimon Glass1-3/+9
Turn on SPI flash support and related commands. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-18x86: Enable USB features for corebootSimon Glass1-0/+17
Enable PCI EHCI, storage, keyboard and Ethernet for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-05x86: Enable CONFIG_OF_CONTROL on corebootSimon Glass1-0/+6
Make use of a device tree on coreboot boards, and set the default to link. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-15x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTORSimon Glass1-1/+0
Invert the polarity of this option to simplify the Makefile logic. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Gabe Black <gabeblack@chromium.org>
2012-12-26x86: coreboot: Enable io commandSimon Glass1-0/+1
Enable the io command for x86 on coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-07x86: Fix coreboot config to boot on ChromebookSimon Glass1-14/+12
The config is current broken. It compiles but does not boot because IDE is enabled. Remove all IDE options, and enable SCSI instead. Also add a working boot command and Linux bootargs, and enable command line editing to make it easier to work with. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-07x86: Turn on support for EFI's GPT in the coreboot configGabe Black1-0/+3
This allows u-boot to figure out the partitions of a chrome-os install. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-07x86: coreboot: Enable video displaySimon Glass1-2/+8
Enable the display on coreboot, using CFB. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-07x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer1-1/+1
This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-07x86: Enable CONFIG_CMD_ZBOOT for corebootSimon Glass1-0/+3
Enable this option to support booting a zImage. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-07x86: Enable ICH6 GPIO controller for corebootSimon Glass1-0/+4
Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-01x86: Define CONFIG_SYS_VSNPRINTF for corebootSimon Glass1-0/+1
This option protects the printf() functions from overflow. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-01x86: Select stdio devices for corebootSimon Glass1-0/+12
We want to support VGA, serial, USB keyboard and the Coreboot memory console buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: coreboot: Enable LPC TPMSimon Glass1-0/+4
Coreboot boards have an LPC TPM connected, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Remove coreboot start16 codeSimon Glass1-1/+1
Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Put global data on the stackGraeme Russ1-3/+2
Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-03x86: config: Enable AHCI support for corebootSimon Glass1-0/+22
Enable AHCI driver for Intel SATA devices. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-22config: Enable CBFS, ext4 for corebootSimon Glass1-0/+3
Enable Coreboot and EXT4 Filesystems on the coreboot board. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-15serial: Remove CONFIG_SERIAL_MULTI from config filesMarek Vasut1-1/+0
Remove any notion of CONFIG_SERIAL_MULTI from board config files. Since CONFIG_SERIAL_MULTI is now enabled by default, it is useless to specify this config option in the board config files. Therefore remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
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